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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • Date May 1988

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Displaying Results 1 - 10 of 10
  • A universal test set for CMOS circuits

    Publication Year: 1988, Page(s):590 - 597
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    A universal test set for CMOS circuits is demonstrated that can be derived from the functional description of the circuit alone. It is shown that for a restricted class of CMOS circuits, the gate-level universal test set (UTSg) consisting of maximal false vectors and minimal true vectors can sensitize every detectable stuck-open fault in the circuit. A universal initialization set (UIS)... View full abstract»

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  • On an improved design approach for C-testable orthogonal iterative arrays

    Publication Year: 1988, Page(s):609 - 615
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    An improved version of the C-testability approach for orthogonal iterative arrays presented by H. Elhuni et al. (see ibid., vol.CAD-5, p.573-81, 1986) is described. C-testability is defined by those criteria which characterize the complexity of the testing process as independent of the dimensions of the array and of the erroneous states of the cells. The proposed approach is based on a cellular au... View full abstract»

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  • NETOPT-a program for multiobjective design of linear networks

    Publication Year: 1988, Page(s):567 - 577
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB)

    A description is given of NETOPT, an interactive program for multiobjective design of linear networks with emphasis on RC active filters. The program section consists of four parts: the analysis program, an optimizer specially designed for network applications, an interface which allows multiobjective minimization, and a part with miscellaneous support functions. After noting the need to ... View full abstract»

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  • An enhanced power meter for SPICE2 circuit simulation

    Publication Year: 1988, Page(s):641 - 643
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    An enhancement to a technique presented by S.M. Kang (IEE J. Solid-State Circuits, vol.SC-21, p.889-91, Oct. 1986) for measuring average power dissipation during a SPICE circuit simulation is described. A modified power meter circuit is discussed that allows power measurement during an arbitrary interval of time, holds a constant final value at the end of the sampling interval, and improves the re... View full abstract»

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  • Verification algorithms for VLSI synthesis

    Publication Year: 1988, Page(s):616 - 640
    Cited by:  Papers (22)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1968 KB)

    A description is given of a theory for, and the application of, a general algorithm for determining whether a given multilevel Boolean function is a tautology or whether two given multilevel Boolean functions are equivalent. Four specific cases of this general algorithm are examined. These are termed the flattening method, the don't-care method, the simulation method, and the algebraic string comp... View full abstract»

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  • Dynamic testability measures for ATPG

    Publication Year: 1988, Page(s):598 - 608
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB)

    Two automatic test pattern generation (ATPG) algorithms, PODEM and FAN, use heuristics that rely on testability measures (TMs). The use of random-pattern (probabilistic) TMs in these heuristics has already been proposed and investigated. The types of TMs proposed for such use are static. Static TMs (STMs) become increasingly unjustifiable as the search for a test pattern progresses. Dynamic TMs (D... View full abstract»

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  • Polynomial splines for MOSFET model approximation

    Publication Year: 1988, Page(s):557 - 566
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    The approximation of MOSFET nonlinearities by use of polynomial splines was investigated for reducing both circuit model development time and model simulation cost. After a brief tutorial on spline functions, it is shown how the number of independent variables for the MOSFET simulation models in digital circuits is reduced by their use. A tableau formulation for generating splines is presented alo... View full abstract»

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  • CAPCAL-a 3-D capacitance solver for support of CAD systems

    Publication Year: 1988, Page(s):549 - 556
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    A program package is presented named CAPCAL that provides a method for calculation of the 3-D electric field distribution due to multilayer metallization of advanced VLSI (very large-scale integration) integrated circuits. The underlying physics and numerical modeling techniques used by CAPCAL are described. The finite-difference method together with a multigrid solver is used to permit easy progr... View full abstract»

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  • Simultaneous signature and syndrome compression

    Publication Year: 1988, Page(s):584 - 589
    Cited by:  Papers (22)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A commonly used organization for built-in self-test of VLSI (very large-scale integration) circuits uses complete or pseudorandom test input generators followed by output data reduction. Two compression techniques which have been used are polynomial division (signature) and ones counting (syndrome). The simultaneous use of both of these approaches in parallel is investigated. Analytic and enumerat... View full abstract»

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  • Hot carrier transport effect in Schottky-barrier diode grown by MBE

    Publication Year: 1988, Page(s):578 - 583
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Hot-electron transport effects in Schottky-barrier diodes grown by molecular-beam epitaxy (MBE) were investigated. Comparisons with experimental results for an Al-n+ GaAs diode shows that terminal currents obtained using the Monte Carlo (MC) method agree well with experiment and are higher than those of conventional analysis for the forward-bias condition. A much higher thermio... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu