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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • Date Apr 1988

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Displaying Results 1 - 11 of 11
  • Automated parameter extraction and modeling of the MOSFET below threshold

    Publication Year: 1988, Page(s):484 - 488
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A subthreshold model for use in circuit simulation software is described. The model includes representation of nonuniform substrate impurity concentrations and short-channel and narrow-channel effects, while being simple in form. It has been developed in concert with an automated parameter-extraction methodology. The model adds only one parameter to the existing strong inversion model with which i... View full abstract»

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  • Fast algorithm for polygon decomposition

    Publication Year: 1988, Page(s):473 - 483
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB)

    An O(klog(k)+n) algorithm is developed, where n is the number of versions, to decompose rectilinear polygons into rectangles. This algorithm uses horizontal cuts only and reports nonoverlapping rectangles the union of which is the original rectilinear polygon. This algorithm has been programmed in Pascal on an Apollo DN320 workstation. Experimentation with recti... View full abstract»

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  • DELIGHT.SPICE: an optimization-based system for the design of integrated circuits

    Publication Year: 1988, Page(s):501 - 519
    Cited by:  Papers (163)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1792 KB)

    DELIGHT.SPICE is the union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program. With the DELIGHT.SPICE tool, circuit designers can take advantage of recent powerful optimization algorithms and a methodology that emphasizes designer intuition and man-machine interaction. Designer and computer are complementary in adjusting parameters of ... View full abstract»

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  • Two-stage channel routing for CMOS gate arrays

    Publication Year: 1988, Page(s):439 - 450
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1140 KB)

    A two-stage channel routing technique for CMOS gate arrays is proposed. In the first stage, certain nets are routed on two sides of the channel so that channel density is reduced. A single-side O(N ) optimum algorithm is presented for this stage. The algorithm can choose one set with maximum weight from among the possible sets of routing nets. The second stage can be general channel routi... View full abstract»

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  • Model selection for SOI MOSFET circuit simulation

    Publication Year: 1988, Page(s):541 - 544
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A method for experimentally selecting proper silicon-on-insulator MOSFET models for circuit simulation is described, verified, and demonstrated. The selection criteria are derived from steady-state current-voltage characteristics predicted by thin-film and (semi-)bulk models. The necessity for proper model selection is emphasized by revealing significant simulation errors that result from seemingl... View full abstract»

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  • Data structuring for process and device simulations

    Publication Year: 1988, Page(s):489 - 500
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    Process and device simulators are becoming more and more complex because of the increasing need for multidimensional simulation of (sub)micrometer structures. Programs must be maintainable because of the high development cost. Moreover, because input and output data may have to be updated, connections between different simulators, and between simulators and graphical pre- and postprocessors, must ... View full abstract»

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  • Two NP-hard interchangeable terminal problems

    Publication Year: 1988, Page(s):467 - 472
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Two subproblems that arise when routing channels with interchangeable terminals are shown to be NP-hard. These problems are: (1) determining whether there is a net-to-terminal assignment that results in an acyclic vertical and constraint graph and (2) for instances with acyclic vertical constraint graphs, obtaining net-to-terminal assignments for which the length of the longest path in the vertica... View full abstract»

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  • Algorithms for optimizing, two-dimensional symbolic layout compaction

    Publication Year: 1988, Page(s):451 - 466
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1404 KB)

    A set of algorithms that implement a technique called Supercompaction is described for two-dimensional compaction layouts. The algorithms minimize a one-dimensional objective function (pitch) by moving objects in the layout in two dimensions. The objective function can be monotonically reduced to a locally minimal value, greatly simplifying search. The algorithms can change the layout by simple mo... View full abstract»

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  • Allocation of multiport memories in data path synthesis

    Publication Year: 1988, Page(s):536 - 540
    Cited by:  Papers (62)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated wi... View full abstract»

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  • On yield consideration for the design of redundant programmable logic arrays

    Publication Year: 1988, Page(s):528 - 535
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    Redundancy techniques have been applied to conventional programmable logic arrays (PLAs) to allow for the repair of defective chips. When the redundancy technique is implemented in a VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area, and the additional spare lines can increase the silicon area and propagation delay. However, if the provided redundancy c... View full abstract»

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  • An MOS transistor charge model for VLSI design

    Publication Year: 1988, Page(s):520 - 527
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described. The total stored charge in each of the gate, bulk, and channel regions is obtained by integrating the distributed charge densities over the thin-oxide area. Charge conservation is guaranteed in this model by using the terminal charges as the state variables. The capacitance ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu