By Topic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • Date Mar 1988

Filter Results

Displaying Results 1 - 12 of 12
  • Design of MOS networks in single-rail input logic for incompletely specified functions

    Publication Year: 1988, Page(s):339 - 345
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    If a logic gate in a logic network of MOS transistors expresses a negative function, which is a logic function that can be expressed as the complement of a disjunctive form of only noncomplemented variables, it is called a negative gate. An algorithm, DIMN, for the design of a MOS logic network with a minimum number of negative gates and irredundant connections among negative gates for a completel... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A parity bit signature for exhaustive testing

    Publication Year: 1988, Page(s):333 - 338
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A parity bit signature particularly well suited for exhaustive testing techniques is defined and discussed. The discussion is concerned not only with the proposed parity bit signature itself, but also with the general problem of evaluating its effectiveness relative to a given implementation. In addition to such desirable properties as uniformity and ease of implementation, it is shown to be espec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of strategies for constructive general block placement

    Publication Year: 1988, Page(s):371 - 377
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    The problem of general block placement in VLSI is considered, using the constructive approach in which blocks are selected and located one at a time. Some well-known strategies are presented for the selection of the next block to be located, novel ones are proposed, and a methodology to evaluate them is established. It is then shown that the optimization problem arising in constructive placement c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Systolic routing hardware: performance evaluation and optimization

    Publication Year: 1988, Page(s):397 - 410
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB)

    The performance of maze-routing algorithms mapped onto linear systolic array hardware is examined. Cell expansions in the wavefront-expansion phase of maze routing are performed in parallel in each processing stage of the hardware as the routing grid streams through the processor array. The authors concentrate on optimizing the performance of single-net routing problems with respect to a given sys... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Conditionally robust two-pattern tests and CMOS design for testability

    Publication Year: 1988, Page(s):325 - 332
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    The concept of a conditionally robust two-pattern test for testing stuck-open transistor faults in CMOS gates is introduced. Such a test is conditionally hazard-free; i.e. the transition will not produce a hazardous output provided a (partial) order is imposed on the time instants at which the components of the input pattern undergo transition. Two sources of the existence of such a partial order ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sehwa: a software package for synthesis of pipelines from behavioral specifications

    Publication Year: 1988, Page(s):356 - 370
    Cited by:  Papers (267)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1264 KB)

    A set of techniques for the synthesis of pipelined data paths is described, and Sehwa, a program that performs such synthesis, is presented. The task includes the generation of data paths from a data-flow graph along with a clocking scheme that overlaps execution of multiple tasks. Some design examples are given. Sehwa can find the minimum-cost design, the highest performance design, and other des... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel standard cell placement algorithms with quality equivalent to simulated annealing

    Publication Year: 1988, Page(s):387 - 396
    Cited by:  Papers (32)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    An algorithm called heuristic spanning creates parallelism by simultaneously investigating different areas of the plausible combinatorial search space. It is used to replace the high-temperature portion of simulated annealing. The low-temperature portion of simulated annealing is sped up by a technique called section annealing, in which placement is geographically divided and the pieces are assign... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits

    Publication Year: 1988, Page(s):346 - 355
    Cited by:  Papers (15)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    CARLOS, a program system for the automated synthesis of random combinational CMOS logic, is described. The input of CARLOS is a specification of a multiple-output Boolean function in the form of a truth table. CARLOS produces an optimized random logic circuit composed of NAND, NOR, and complex gates under the given fan-in and fan-out limitations. The algorithms implemented in CARLOS are based on l... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Model and solution strategy for placement of rectangular blocks in the Euclidean plane

    Publication Year: 1988, Page(s):378 - 386
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    The authors describe a nonlinear optimization model for the placement of rectangular blocks with some wire connections among them in the Euclidean plane, so that the total wire length is minimized. Such a placement algorithm is useful as a CAD tool for VLSI and printed-circuit-board layout designs. The model ensures that the blocks will not overlap and minimizes the sum of the distances of the int... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A normalized-area measure for VLSI layouts

    Publication Year: 1988, Page(s):411 - 419
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    A figure of merit called normalized-area, is introduced for the purpose of evaluating layouts for VLSI networks. This measure is distinctly different from the existing VLSI measures in two major aspects: (1) it expresses the utilization of the layout area by revealing the constant factor hidden in its asymptotic area-complexity; and (2) it distinguishes between node and wire sizes. Normalized-area... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimization of the number of layers for single row routing with fixed street capacity

    Publication Year: 1988, Page(s):420 - 424
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    A set of three algorithms is presented for solving single-row routine problems with a fixed street capacity using the least number of layers. The main difference among these algorithms is in the strategy used to search for an optimal solution, which greatly affects the performance. At the extreme points of the strategy are algorithms Q and S. The worst-case time complexity is linear for algorithm ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-voltage device modeling for SPICE simulation of HVIC's

    Publication Year: 1988, Page(s):425 - 432
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    A novel methodology for flexible SPICE implementation of physical models for high-voltage power devices, accounting for their unique characteristics, is presented and demonstrated. The implementation is achieved without modifying the simulator code by utilizing user-defined controlled sources that reference a subroutine that defines the system of model equations. The simultaneous solution of the e... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu