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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 3 • Date Mar 1988

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Displaying Results 1 - 12 of 12
  • Design of MOS networks in single-rail input logic for incompletely specified functions

    Publication Year: 1988 , Page(s): 339 - 345
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    If a logic gate in a logic network of MOS transistors expresses a negative function, which is a logic function that can be expressed as the complement of a disjunctive form of only noncomplemented variables, it is called a negative gate. An algorithm, DIMN, for the design of a MOS logic network with a minimum number of negative gates and irredundant connections among negative gates for a completely specified function was published by the authors in 1985. DIMN is extended here to the case of an incompletely specified function, and an example is given View full abstract»

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  • Model and solution strategy for placement of rectangular blocks in the Euclidean plane

    Publication Year: 1988 , Page(s): 378 - 386
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    The authors describe a nonlinear optimization model for the placement of rectangular blocks with some wire connections among them in the Euclidean plane, so that the total wire length is minimized. Such a placement algorithm is useful as a CAD tool for VLSI and printed-circuit-board layout designs. The model ensures that the blocks will not overlap and minimizes the sum of the distances of the interconnections of the blocks with respect to their orientation as well as their position. Mechanisms are presented for solving more restrictive placement problems, including one in which there is a set of equally spaced, discrete angles to be used in the placement. The mathematical model is based on the Lennard-Jones 6-12 potential equation, on a sine-wave-shaped penalty function, and on minimizing the sum of the squares of the Euclidean distances of the block interconnections. Experimental results are presented to show that good placements are achieved with these techniques View full abstract»

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  • CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits

    Publication Year: 1988 , Page(s): 346 - 355
    Cited by:  Papers (12)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    CARLOS, a program system for the automated synthesis of random combinational CMOS logic, is described. The input of CARLOS is a specification of a multiple-output Boolean function in the form of a truth table. CARLOS produces an optimized random logic circuit composed of NAND, NOR, and complex gates under the given fan-in and fan-out limitations. The algorithms implemented in CARLOS are based on logic minimization, novel multiple-output multilevel factoring strategies, and recursive technology mapping. The factorization algorithm performs multiple-output synthesis using an algebraic representation of multiple-output Boolean functions. Tests on a large set of examples have shown the efficiency of the synthesis in terms of circuit size as well as computation time. CARLOS is an integral part of a larger CAD system that supports the automatic logic and physical design of finite-state machines under gate-array constraints View full abstract»

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  • A normalized-area measure for VLSI layouts

    Publication Year: 1988 , Page(s): 411 - 419
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    A figure of merit called normalized-area, is introduced for the purpose of evaluating layouts for VLSI networks. This measure is distinctly different from the existing VLSI measures in two major aspects: (1) it expresses the utilization of the layout area by revealing the constant factor hidden in its asymptotic area-complexity; and (2) it distinguishes between node and wire sizes. Normalized-area is valuable in evaluating alternative layouts for a given structure as well as in analyzing the area utilization of a particular layout for that structure in an absolute sense. An analysis of the normalized-area of the layout schemes for regular structures proposed in the literature shows that most of these schemes are infeasible in practice. Array realizations for several well-known regular structures are used to demonstrate the usefulness of the normalized-area measure. Some practical guidelines for placement and routing to achieve good area utilization in a VLSI chip are presented View full abstract»

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  • Sehwa: a software package for synthesis of pipelines from behavioral specifications

    Publication Year: 1988 , Page(s): 356 - 370
    Cited by:  Papers (228)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1264 KB)  

    A set of techniques for the synthesis of pipelined data paths is described, and Sehwa, a program that performs such synthesis, is presented. The task includes the generation of data paths from a data-flow graph along with a clocking scheme that overlaps execution of multiple tasks. Some design examples are given. Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space. Sehwa is written in Franz Lisp and executes within minutes, for problems of practical size, on a VAX 11/750 View full abstract»

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  • Conditionally robust two-pattern tests and CMOS design for testability

    Publication Year: 1988 , Page(s): 325 - 332
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    The concept of a conditionally robust two-pattern test for testing stuck-open transistor faults in CMOS gates is introduced. Such a test is conditionally hazard-free; i.e. the transition will not produce a hazardous output provided a (partial) order is imposed on the time instants at which the components of the input pattern undergo transition. Two sources of the existence of such a partial order are identified: (1) when a set of transistors is controlled by the same logic signal, the symbolic layout (routing) information provides the knowledge of such a partial order; and (2) multipattern tests, which may be necessary to test embedded CMOS gates, can be looked upon as two-pattern tests with an imposed partial order. Algorithms are given to determine whether a two-pattern test is conditionally hazard-free under a given partial order and to compute minimal cardinality partial orders that, when imposed on a transition, make it conditionally hazard-free View full abstract»

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  • Minimization of the number of layers for single row routing with fixed street capacity

    Publication Year: 1988 , Page(s): 420 - 424
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    A set of three algorithms is presented for solving single-row routine problems with a fixed street capacity using the least number of layers. The main difference among these algorithms is in the strategy used to search for an optimal solution, which greatly affects the performance. At the extreme points of the strategy are algorithms Q and S. The worst-case time complexity is linear for algorithm Q and exponential for algorithm S. The best-case time complexity of all the algorithms is linear. The main disadvantage of algorithm Q is that the constant associated with its time complexity bounds is large. On the other hand, the constant associated with the best-case time complexity bound for algorithm S is small. An experimental evaluation of the performance of the algorithms is presented View full abstract»

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  • Parallel standard cell placement algorithms with quality equivalent to simulated annealing

    Publication Year: 1988 , Page(s): 387 - 396
    Cited by:  Papers (29)  |  Patents (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    An algorithm called heuristic spanning creates parallelism by simultaneously investigating different areas of the plausible combinatorial search space. It is used to replace the high-temperature portion of simulated annealing. The low-temperature portion of simulated annealing is sped up by a technique called section annealing, in which placement is geographically divided and the pieces are assigned to separate processors. Each processor generates simulated-annealing-style moves for the cells in its area and communicates the moves to other processors as necessary. Heuristic spanning and section annealing are shown experimentally to converge to the same final cost function as regular simulated annealing. These approaches achieve significant speedup over uniprocessor simulated annealing, giving high-quality VLSI placement of standard cells in a short period of time View full abstract»

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  • Analysis of strategies for constructive general block placement

    Publication Year: 1988 , Page(s): 371 - 377
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    The problem of general block placement in VLSI is considered, using the constructive approach in which blocks are selected and located one at a time. Some well-known strategies are presented for the selection of the next block to be located, novel ones are proposed, and a methodology to evaluate them is established. It is then shown that the optimization problem arising in constructive placement can be reduced to several much simpler sub problems. Objective functions for locating the selected block to achieve a good layout are presented for three different metrics: the squared Euclidean, rectilinear, and Euclidean. Appropriate optimization problems are obtained and solved analytically, using efficient computation schemes. These solutions have been implemented and are used in a real VLSI chip design environment. It is shown that the squared Euclidean and the rectilinear metrics are preferable to the Euclidean one View full abstract»

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  • Systolic routing hardware: performance evaluation and optimization

    Publication Year: 1988 , Page(s): 397 - 410
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1304 KB)  

    The performance of maze-routing algorithms mapped onto linear systolic array hardware is examined. Cell expansions in the wavefront-expansion phase of maze routing are performed in parallel in each processing stage of the hardware as the routing grid streams through the processor array. The authors concentrate on optimizing the performance of single-net routing problems with respect to a given systolic hardware configuration. A heuristic called constant-increment framing is introduced as a simple method for scheduling all the required wavefront expansion steps on a pipeline of processors. One-layer and two-layer routers using this heuristic have been implemented on a prototype systolic processor. Experimental and theoretical comparisons suggest that the constant-increment heuristic exhibits performance within a factor of two of optimal over a range of hardware configurations, and is substantially easier to compute than the optimal solution View full abstract»

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  • A parity bit signature for exhaustive testing

    Publication Year: 1988 , Page(s): 333 - 338
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    A parity bit signature particularly well suited for exhaustive testing techniques is defined and discussed. The discussion is concerned not only with the proposed parity bit signature itself, but also with the general problem of evaluating its effectiveness relative to a given implementation. In addition to such desirable properties as uniformity and ease of implementation, it is shown to be especially amenable to efficient fault coverage calculations View full abstract»

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  • High-voltage device modeling for SPICE simulation of HVIC's

    Publication Year: 1988 , Page(s): 425 - 432
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    A novel methodology for flexible SPICE implementation of physical models for high-voltage power devices, accounting for their unique characteristics, is presented and demonstrated. The implementation is achieved without modifying the simulator code by utilizing user-defined controlled sources that reference a subroutine that defines the system of model equations. The simultaneous solution of the equations, which describe the integrated charges in the device and the quasistatic terminal currents in the terms of the terminal voltages, is effected by the SPICE2 nodal analysis. The methodology is exemplified by modeling the insulated-gate transistor (IGT). SPICE simulations of DC and transient characteristics of IGT switching circuits are discussed and shown to be representative of measurements. The flexibility of the modeling methodology for high-voltage integrated-circuit (HVIC) CAD is demonstrated by simulating effects of both static and dynamic latch-up in the merged bipolar/MOS structure of the IGT View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu