By Topic

Electron Device Letters, IEEE

Issue 2 • Date Feb. 2000

Filter Results

Displaying Results 1 - 10 of 10
  • Metamorphic In/sub 0.53/Ga/sub 0.47/As/In/sub 0.52/Al/sub 0.48/As HEMTs on germanium substrates

    Page(s): 57 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (48 KB)  

    We report for the first time the successful epitaxial growth and processing of high-performance metamorphic high electron mobility transistors (HEMTs) on Ge substrates, with a transconductance of 700 mS/mm and a saturation channel current of 650 mA/mm. To reduce parasitic capacitances due to the conductive substrate, a dry etch method based on CF4 and O2 reactive ion etching (RIE) is developed for selective substrate removal. Devices with 0.2 μm gate length display an increase of the extrinsic cut-off frequency fT from 45 GHz before, to 75 GHz after substrate removal, whereas the maximum oscillation frequency fmax increases from 68 GHz to 95 GHz. Based on this excellent rf performance level, in combination with the highly selective thinning process, we think that Ge as a sacrificial substrate is a promising candidate for the integration of thinned individual HEMTs with passive circuitry on low-cost substrates. This could result in low-cost advanced hybrid systems for mass-market millimeter wave applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Microwave power performance comparison between single and dual doped-channel design in AlGaAs/InGaAs HFETs

    Page(s): 60 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (101 KB)  

    Single and dual doped-channel AlGaAs/InGaAs FETs (DCFETs) were fabricated, characterized, and compared with each other in terms of dc, rf, and power performance. The dual doped channel design provides a higher current density, and a better linear operation range over a wide gate bias range and frequency. A 1 μm-long gate dual-DCFET operated at 1.9 GHz demonstrates a power-added efficiency of 51.5%, a gain of 19 dB, and an output power density of 305 mW/mm at 2.5 V. This performance suggests that dual doped-channel design is more suitable for linear and high power microwave device applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor

    Page(s): 63 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (52 KB)  

    We report on the AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (MOS-HFET) and present the results of the comparative studies of this device and a base line AlGaN/GaN heterostructure field effect transistor (HFET). For a 5-μ source-to-drain opening, the maximum current was close to 600 mA/mm for both devices. The gate leakage current for the MOS-HFET was more than six orders of magnitude smaller than for the HFET. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Highly uniform and low turn-on voltage Si field emitter arrays fabricated using chemical mechanical polishing

    Page(s): 66 - 69
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (94 KB)  

    Turn-on voltage of about 30 V is observed in 1-μm gate-aperture Si field emitter arrays fabricated using oxidation sharpening and chemical mechanical polishing. Small emitter tip radius (/spl sim/10 nm) was achieved from low temperature oxidation sharpening. The gate leakage current is observed to be less than 0.01% of emitter current over the range of measurement. Devices show excellent emission uniformity for different sized arrays. Current saturation was observed at high gate voltages because of low dopant concentration of the substrate. Below the saturation region, the current-voltage characteristics obey the Fowler-Nordheim field emission theory. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Poly-Si thin-film transistors on steel substrates

    Page(s): 70 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (67 KB)  

    We report the successful fabrication of poly-Si thin-film transistors (TFTs) on stainless steel substrates. The TFTs were fabricated on a 500 μm thick polished stainless steel substrate using furnace crystallized amorphous Si deposited by PECVD. These devices typically have threshold voltages of 8.6 V, linear effective mobilities of 6.2 cm2/V/spl middot/s and subthreshold slopes of 0.93 decade/V. This work demonstrates the feasibility of poly-Si TFTs on stainless steel substrates and identifies some critical issues involved in poly Si processing on stainless steel. This will enable the fabrication of arrays with integrated drivers on a cheap, flexible and durable substrate for various displays and other large area array microelectronic applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Plasma hydrogenation of metal-induced laterally crystallized thin film transistors

    Page(s): 73 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (50 KB)  

    The device characteristics of conventional metal-induced laterally crystallized thin film transistors (MILC-TFT's) are adversely affected by the existence of the continuous grain boundaries in the depletion regions of the metallurgical source and drain junctions. It has been shown that by introducing an extra lithographic masking step, the detrimental effects can be eliminated by separating the grain boundaries from the junction depletion regions. In this work, it is demonstrated that the traps in these grain boundaries can also be efficiently passivated using simple plasma hydrogenation, resulting in simultaneous improvements in the threshold voltage, the subthreshold slope, the mobility, the drain breakdown voltage, and the leakage current. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The effects of interfacial sub-oxide transition regions and monolayer level nitridation on tunneling currents in silicon devices

    Page(s): 76 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (62 KB)  

    Direct tunneling (D-T) in Si metal-oxide-semiconductor (MOS) devices having 1.8 to 3 nm thick gate oxides is reduced approximately tenfold by monolayer Si-dielectric interface nitridation with respect to devices with nonnitrided interfaces. The reduction is independent of gate oxide-equivalent thickness, and gate or substrate injection, and extends into the Fowler-Nordheim tunneling (F-N-T) regime for thicker oxides as well. A barrier layer model, including sub-oxide transition regions, has been developed for the interface electronic structure for tunneling calculations using X-ray photoelectron spectroscopy data. These calculations provide a quantitative explanation for the observed tunneling current reductions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sub-100 nm /spl Gamma/-gate MOSFETs with self-aligned drain extension formed by solid phase diffusion

    Page(s): 79 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB)  

    High performance 60 nm /spl Gamma/-gate n-MOSFETs have been fabricated. The very fine poly-Si gates were made using deposition and etchback of poly-Si to form a sidewall along the conductive poly-Si/PSG dummy stack. Due to the relatively wide dummy stack, the low gate resistance r/sub g/ is independent of the actual gate length; this is especially essential for rf circuits as high gate resistance could severely degrade high frequency performance. The diffusion source, PSG layer underneath the poly-Si, allowed the formation of an ultra-shallow self-aligned drain extension by solid phase diffusion. Together with a steep retrograde channel using indium, good subthreshold characteristics as well as high current drive were obtained. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A LDMOS technology compatible with CMOS and passive components for integrated RF power amplifiers

    Page(s): 82 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB)  

    The authors describe a bulk silicon LDMOS technology, which is compatible with CMOS and passive components, for the implementation of RF integrated power amplifiers (IPA's) used in portable wireless communication applications. This technology allows complete integration of the low cost and low power front-end circuits with the baseband circuits for single-chip wireless communication systems. The LDMOS transistor (0.35 μm channel length, 3.85 μm drift length, 3 GHz fT and 20 V breakdown voltage), CMOS transistors (1.5 μm channel length), and high Q-factor (up to 6.10 at 900 MHz and 7.14 at 1.8 GHz) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The dependence of channel length on channel width in narrow-channel CMOS devices for 0.35-0.13 μm technologies

    Page(s): 85 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (62 KB)  

    We have found that narrow-channel PFET's do not have the same effective channel length as wide PFET's with the same polysilicon length. Narrow PFET devices are longer than their wide counterparts by 20-40 nm while narrow NFET devices are negligibly different from wide NFET's. This phenomenon occurs in a wide variety of technologies, from 0.13 and 0.18 μm technologies with extension/halo devices to a 0.35-μm technology with simple abrupt-junction devices. Depending on the details of the short-channel rolloff behavior, this phenomenon may result in apparent anomalous narrow-channel threshold voltage behavior. We suggest that the modification of the boron redistribution by the mechanical stress imposed by the bounding isolation SiO2 may explain the effect. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Amitava Chatterjee