Scheduled System Maintenance
On Friday, October 20, IEEE Xplore will be unavailable from 9:00 PM-midnight ET. We apologize for the inconvenience.
Notice: There is currently an issue with the citation download feature. Learn more.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 1 • Feb. 2000

Filter Results

Displaying Results 1 - 12 of 12
  • HML, a novel hardware description language and its translation to VHDL

    Publication Year: 2000, Page(s):1 - 8
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    We present hardware ML (HML), an innovative hardware description language (HDL) based on the functional programming language SML. Features of HML not found in other HDL's include polymorphic types and advanced type checking and type inference techniques. We have implemented an HML type checker and a translator for automatically generating VHDL from HML descriptions. We generate a synthesizable sub... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solving covering problems using LPR-based lower bounds

    Publication Year: 2000, Page(s):9 - 17
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (129 KB)

    Unate and binate covering problems are a subclass of general integer linear programming problems with which several problems in logic synthesis, such as two-level logic minimization and technology mapping, are formulated. Previous branch-and-bound methods for solving these problems exactly use lower bounding techniques based on finding maximal independent sets. In this paper, we examine lower boun... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power modeling for high-level power estimation

    Publication Year: 2000, Page(s):18 - 29
    Cited by:  Papers (76)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB)

    In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-l... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel and efficient routing architecture for multi-FPGA systems

    Publication Year: 2000, Page(s):30 - 39
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (166 KB)

    Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and field-programmable interconnect devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed, and previous research has shown that the parti... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cut-based functional debugging for programmable systems-on-chip

    Publication Year: 2000, Page(s):40 - 51
    Cited by:  Papers (4)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB)

    Due to the growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip (SOC). Traditional approaches, such as system emulation and simulation, are becoming increasingly inadequate to address the system debugging needs. Design simulation is two to ten orders of magnitude slower than emulation and, thus,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An adaptive fuzzy logic controller: its VLSI architecture and applications

    Publication Year: 2000, Page(s):52 - 60
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    Most previous work about the hardware design of a fuzzy logic controller (FLC) intended to either improve its inference performance for real-time applications or to reduce its hardware cost. To our knowledge, there has been no attempt to design a hardware FLC that can perform an adaptive fuzzy inference for the applications of on-line adaptation. The purpose of this paper is to present such an ada... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Estimation for maximum instantaneous current through supply lines for CMOS circuits

    Publication Year: 2000, Page(s):61 - 73
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (270 KB)

    We present new techniques for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. We investigate four different approaches: (1) timed-ATPG-based approach; (2) probability-based approach; (3) genetic algorithm-based approach; and (4) integer linear programming (ILP) approach. The first three approaches produce a tight lower bound on the maximum current. Th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of custom interleaved memory systems

    Publication Year: 2000, Page(s):74 - 83
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    This paper presents a novel approach to the synthesis of interleaved memory systems that is especially suited for application-specific processors. Our synthesis system generates the optimized interleaved memories for a specific algorithm and finds the best mapping of arrays in that algorithm onto the memory system to achieve high performance. The design space is four-dimensional (4-D) and comprise... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Speed and area tradeoffs in cluster-based FPGA architectures

    Publication Year: 2000, Page(s):84 - 93
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB)

    One way to reduce the delay and area of field-programmable gate arrays (FPGAs) is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnections. In this paper, we empirically evaluate FPGA architectures with logic clusters ranging in size from 1 to 20, and show that compared to architectures with size 1 clusters, ar... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance energy-efficient D-flip-flop circuits

    Publication Year: 2000, Page(s):94 - 98
    Cited by:  Papers (35)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    This paper investigates performance, power, and energy efficiency of several CMOS master-slave D-flip-flops (DFF's). To improve performance and energy efficiency, a push-pull DFF and a push-pull isolation DFF are proposed. Among the five DFF's compared, the proposed push-pull isolation circuit is found to be the fastest with the best energy efficiency. Effects of using a double-pass-transistor log... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of VHDL-based totally self-checking finite-state machine and data-path descriptions

    Publication Year: 2000, Page(s):98 - 103
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (139 KB)

    This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. T... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Two systolic architectures for modular multiplication

    Publication Year: 2000, Page(s):103 - 107
    Cited by:  Papers (26)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (173 KB)

    The authors present two systolic architectures to speed up the computation of modular multiplication in RSA cryptosystems. In the double-layer architecture, the main operation of Montgomery's algorithm is partitioned into two parallel operations after using the precomputation of the quotient bit. In the non-interlaced architecture, we eliminate the one-clock-cycle gap between iterations by pairing... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu