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Micro, IEEE

Issue 1 • Date Jan/Feb 2000

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Displaying Results 1 - 8 of 8
  • Classifying packets with hierarchical intelligent cuttings

    Page(s): 34 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    Increasing demands on Internet router performance and functionality create a need for algorithms that classify packets quickly with minimal storage requirements and allow frequent updates. Unlike previous algorithms, the algorithm proposed here meets this need well by using heuristics that exploit structure present in classifiers. Our approach, which we call HiCuts (hierarchical intelligent cuttings), attempts to partition the search space in each dimension, guided by simple heuristics that exploit the classifier's structure. We discover this structure by preprocessing the classifier. We can tune the algorithm's parameters to trade off query time against storage requirements. In classifying packets based on four header fields, HiCuts performs quickly and requires relatively little storage compared with previously described algorithms View full abstract»

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  • An empirical analysis of the IEEE-1394 serial bus protocol

    Page(s): 58 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    The statistics collector and analyzer records, displays, and analyzes performance measurements from an active IEEE-1394 bus in real time. An empirical analysis using SCA exposes the unique, complex arbitration mechanisms used by IEEE-1394 nodes and their effect on the performance of higher level protocols View full abstract»

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  • A scheduler ASIC for a programmable packet switch

    Page(s): 42 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB)  

    While the Internet is successful in supporting traditional data-only traffic, an integrated services Internet is inevitable with the emergence of new applications such as voice, video, multimedia, and interactive video conferencing. Such an integrated services network should support a wide range of applications with diverse quality of service requirements and traffic characteristics. Provision for quality of service in packet networks in general, and in the Internet in particular, is the focus of most of the recent developments in switching and routing system design. We designed a generic, single-queue scheduler engine for use in a programmable packet switch/router to handle IP packets, ATM cells, or a combination of both. Comprising 275,000 gates, the 0.35-micron ASIC is incorporated into a prototype programmable packet switch View full abstract»

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  • Cache memory design for Internet processors

    Page(s): 28 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    As a result of the exploding bandwidth demand from the Internet, network router and switch designers are designing and fabricating a growing number of microchips specifically for networking devices rather than traditional computing applications. In particular, a new breed of microprocessors, called Internet processors, has emerged that is designed to efficiently execute network protocols on various types of internetworking devices including switches, routers, and application-level gateways. We evaluate a series of three progressively more aggressive routing-table cache designs and demonstrate that the incorporation of hardware caches into Internet processors, combined with efficient caching algorithms can significantly improve overall packet forwarding performance View full abstract»

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  • Authenticating network attached storage

    Page(s): 49 - 57
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    We present an architecture for network-authenticated disks that implements distributed file systems without file servers or encryption. Our system provides network clients with direct network access to remote storage View full abstract»

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  • The TigerSHARC DSP architecture

    Page(s): 66 - 76
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    This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 MFLOPS (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point) View full abstract»

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  • Solving interconnection problems

    Page(s): 15 - 17
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  • Architectural considerations for CPU and network interface integration

    Page(s): 18 - 26
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    The authors describe UNUM, an architecture for integrating communications functionality into the CPU. UNUM not only simplifies the design of communications processors but also improves their performance and provides them with greater flexibility. With these capabilities, functions typically performed in cuscom hardware can be moved to software executing on the main CPU View full abstract»

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High-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems.

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Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center