IEEE Design & Test of Computers

Issue 1 • Feb. 1990

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Displaying Results 1 - 4 of 4
  • Designing and implementing an architecture with boundary scan

    Publication Year: 1990, Page(s):9 - 19
    Cited by:  Papers (12)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (693 KB)

    A description is given of a standardized structured test methodology based on the boundary-scan proposal from the Joint Test Action Group (JTAG), which is now IEEE proposed standard P1149.1. Boundary scan does not address testability at the IC level, primarily because there is no standard for designing built-in self-testing (BIST) circuits. An architecture called the hierarchical testable, or H-te... View full abstract»

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  • Contactless, high-speed waveform measurements on gallium arsenide ICs

    Publication Year: 1990, Page(s):20 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (568 KB)

    A setup for photoemission testing, which compares favorably with results from electron-beam testing, particularly in terms of measurement time, is presented. The photoemission sampling system described has a unique detector design and a viewer for the added convenience of the equipment operator. performance results when this technique is used to measure delay and rise times on integrated gallium a... View full abstract»

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  • Test generation for current testing (CMOS ICs)

    Publication Year: 1990, Page(s):26 - 38
    Cited by:  Papers (106)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (907 KB)

    Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on-chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-... View full abstract»

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  • Using a test-specification format in automatic test-program generation

    Publication Year: 1990, Page(s):39 - 45
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (544 KB)

    The author suggests that if the information necessary for testing a digital IC or printed-circuit board is kept and transferred in a standardized format, testing will be much easier. He describes the concept of a test-specification format (TSF) and reports the results of experiments with two candidate TSFs. The first, Tandem, is a restricted implementation that uses ITF, aPhilips internal language... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty