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Solid-State Circuits, IEEE Journal of

Issue 1 • Date Jan. 2000

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Displaying Results 1 - 17 of 17
  • Analog ALC crystal oscillators for high-temperature applications

    Publication Year: 2000 , Page(s): 2 - 14
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (257 KB)  

    Fundamental mode and third-harmonic mode integrated high-performance automatic level controlled (ALC) crystal oscillators for high-temperature applications (up to 250/spl deg/C), are described in this paper. These oscillators were designed for a pressure measurement system in high-temperature environments, where the output signal is the difference between both generated frequencies. Frequency variations smaller than 0.0001 ppm/s for each oscillator and a frequency drift of about 2.5 ppm/year of the frequency difference are the measured performance concerning, respectively, the short-term (1 s) and long-term frequency stability of these integrated high performance crystal oscillators over the 30/spl deg/C-225/spl deg/C temperature range. Other important characteristics are the very stable and constant oscillation levels (/spl sim/1.1 Vpp), the small second-harmonic distortion (/spl sim/60 dR), and the phase noise (/spl sim/95 dB at 50 kHz shift). The characteristics of these oscillators make them also suitable for many other measurement systems (time, temperature, and other physical and chemical quantities), especially if they are constrained to operate under severe temperature conditions. View full abstract»

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  • Noise in RF-CMOS mixers: a simple physical model

    Publication Year: 2000 , Page(s): 15 - 25
    Cited by:  Papers (277)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    Flicker noise in the mixer of a zero- or low-intermediate frequency (IF) wireless receiver can compromise overall receiver sensitivity. A qualitative physical model has been developed to explain the mechanisms responsible for flicker noise in mixers. The model simply explains how frequency translations take place within a mixer. Although developed to explain flicker noise, the model predicts white noise as well. Simple equations are derived to estimate the flicker and white noise at the output of a switching active mixer. Measurements and simulations validate the accuracy of the predictions, and the dependence of mixer noise on local oscillator (LO) amplitude and other circuit parameters. View full abstract»

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  • Active capacitor multiplier in Miller-compensated circuits

    Publication Year: 2000 , Page(s): 26 - 32
    Cited by:  Papers (94)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    A technique is presented whereby the compensating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads. Reducing physical area requirements while producing the same or perhaps better performance is especially useful in complex systems where most, if not all, functions are integrated onto a single integrated circuit. Die area in such systems is a luxury. The increasing demand for mobile battery-operated devices is a driving force toward higher integration. The enhanced Miller-compensation technique developed in this paper helps enable higher integration while being readily applicable to any process technology, be it CMOS, bipolar, or BiCMOS. Furthermore, the technique applies, in general, to amplifier circuits in feedback configuration. Experimentally, the integrated linear regulator (fabricated in a 1-/spl mu/m BiCMOS process technology) proved to be stable for a wide variety of loading conditions: load currents of up to 200 mA, equivalent series resistance of up to 3 /spl Omega/, and load capacitors ranging from 1.5 nF to 20 /spl mu/E The total quiescent current flowing through the regulator was less than 30 /spl mu/A during zero load-current conditions. View full abstract»

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  • 1-V rail-to-rail operational amplifiers in standard CMOS technology

    Publication Year: 2000 , Page(s): 33 - 44
    Cited by:  Papers (44)  |  Patents (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB)  

    The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-/spl mu/m CMOS process. Experimental results are provided and the corresponding performances are discussed and compared. View full abstract»

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  • A stereo audio chip using approximate processing for decimation and interpolation filters

    Publication Year: 2000 , Page(s): 45 - 55
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB)  

    A stereo audio chip uses approximate processing techniques in the digital decimation and interpolation filters to reduce its active power dissipation. One pair of analog-to-digital (A/D) converters and one pair of digital-to-analog (D/A) converters have been integrated in a die area of 10.22 mm/sup 2/ in a 0.5 /spl mu/m CMOS technology. The total power dissipation of these converters without power management is 200 mW when operated from a 5-V power supply. When the signal is fully active, power reductions of 36% for decimation and 17% for interpolation over fixed-order filters are demonstrated. When the signal is 40 dB below overload, power reductions of 67% for decimation and 44% for interpolation over fixed-order filters are observed. The power reductions are 83.1% for A/D converters, and 82.7% for D/A converters, when the signal is silent for a period of time. View full abstract»

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  • A CMOS analog timing recovery circuit for PRML detectors

    Publication Year: 2000 , Page(s): 56 - 65
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    A fully integrated analog timing recovery circuit for partial-response maximum-likelihood (PRML) detectors for digital magnetic storage is described. The circuit uses a decision-directed minimum mean-squared error (MMSE) algorithm and achieves phase acquisition within 100-bit periods at a maximum speed of 180 Mb/s. It dissipates 76 mW from a single 3.3-V supply and has an active die area of 1.8 mm/sup 2/ in a 1.2-/spl mu/m CMOS process. At 180 Mb/s, the rms clock fitter is 15 ps and peak-to-peak jitter is 97 ps. The test results demonstrate the feasibility of an analog CMOS implementation of decision-directed MMSE timing recovery for PRML detectors. View full abstract»

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  • A multigigahertz Josephson-semiconductor interface circuit using 77-K differential monolithic HEMT amplifier and 4.2-K JJ high-voltage driver for superconductor-semiconductor electronic hybrid systems

    Publication Year: 2000 , Page(s): 66 - 73
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (161 KB)  

    We proposed and successfully demonstrated a high-speed Josephson IC to semiconductor IC output interface circuit combining a high electron mobility transistor (HEMT) amplifier and Josephson high-voltage drivers successfully. We developed a 0.5-/spl mu/m gate 77-K wide-band analog monolithic HEMT amplifier for the interface. The HEMT device consisted of InGaP/InGaAs materials stable even at 77 K. The amplifier has a differential amplifier as a first stage to cancel out ground-level fluctuations in the Josephson IC and showed a voltage gain of 23 dB and /spl sim/3-dB frequency of 8 GHz. A 0.63-V/sub p-p/ output was obtained from a 5-GHz, 30-mV/sub p-p/ complementary input signal. We succeeded in transfer ring a voltage signal from 10-stack Josephson high-voltage drivers to a 50-/spl Omega/ system at room temperature with 0.7-V/sub p-p/ amplitude at 300-MHz clock using the HEMT amplifier. View full abstract»

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  • A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers

    Publication Year: 2000 , Page(s): 74 - 84
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (314 KB)  

    This paper describes a new low-power design concept appropriate for column drivers of high-resolution active matrix liquid crystal displays with a dot inversion method. The proposed multi-level multiphase charge-recycling method reduces power consumption incurred in driving highly capacitive column lines by storing the charge into the external capacitors and reusing it in the next cycle. With the proposed method, power consumption can be reduced asymptotically to zero with the infinite number of storage capacitors. However it is also shown that total power reduction can be counterbalanced by the power consumption in driving switches used in the recycling process. Analytical equations, simulation results, and measurement results from an experimental chip are shown to validate the proposed method. Dynamic power reduction of 55%-70% is measured with a three-level five-phase charge-recycling method compared with a conventional column driver. View full abstract»

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  • CMOS stress sensors on [100] silicon

    Publication Year: 2000 , Page(s): 85 - 95
    Cited by:  Papers (59)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (242 KB)  

    CMOS analog stress sensor circuits based upon the piezoresistive behavior of MOSFET's are presented. On the [100] surface, these circuits provide temperature-compensated outputs that are proportional to the in-plane normal stress difference (/spl sigma/(11)'-/spl sigma//sub 22/') and the in-plane shear stress /spl sigma//sub 22/'. The circuits provide high sensitivity to stress, well-localized stress-state measurement, and direct voltage or current outputs that eliminate the need for tedious /spl Delta/R/R measurements required with more traditional resistor rosettes. The theoretical and experimental results also provide design guidance for calculating and minimizing the sensitivity of traditional analog circuits to packaging-induced die stress. View full abstract»

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  • Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's

    Publication Year: 2000 , Page(s): 96 - 99
    Cited by:  Papers (23)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (97 KB)  

    This paper deals with the Single Sideband to Carrier Ratio (SSCR) dependence on the oscillation amplitude of a fully integrated LC-tuned voltage-controlled oscillator, fabricated in high-speed bipolar technology. As the oscillation amplitude increases, the SSCR reaches a minimum and then steeply rises, setting a limit to the range where better performance can be traded against higher power dissipation. This dependence is fully explained by taking into account that noise and disturbances modulate the phase delay due to the active elements. Experimental and simulation procedures for the evaluation of this effect are presented and their impact on the circuit performance is discussed. View full abstract»

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  • A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset

    Publication Year: 2000 , Page(s): 100 - 103
    Cited by:  Papers (24)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (96 KB)  

    A packaged 1.1-GHz CMOS voltage-controlled oscillator (VCO) with measured phase noise of -92, -112, and -126 dBc/Hz at 10-, 100-, and 600-kHz offsets is demonstrated. According to J. Craninekx et al. (1997), these satisfy the GSM requirements. The extrapolated phase noise at a 3 MHz offset is -140 dBc/Hz. The power consumption is 6.8 and 12.7 mW at V/sub DD/=1.5 and 2.7 V, respectively. The VCO is implemented in a low-cost 0.8-/spl mu/m foundry CMOS process, which uses p+ substrates with a p-epitaxial layer. Buried channel PMOS transistors are exclusively used for lower 1/f noise. The inductors for the LC tanks are implemented using a series combination of an on-chip spiral inductor, four bond wires, and two package leads to increase Q. This technique requires no extra board space beyond that needed for the additional package leads. View full abstract»

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  • A 71-MHz CMOS IF-baseband strip for GSM

    Publication Year: 2000 , Page(s): 104 - 108
    Cited by:  Papers (19)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (121 KB)  

    An intermediate-frequency (IF) baseband strip for a superheterodyne GSM receiver developed in a 0.25-/spl mu/m CMOS technology is presented. It contains a 71-MHz IF amplifier, programmable between -20 and +60 dB in 2-dB steps; a quadrature demodulator; and two low-pass output filters for channel selection. Measurements show an overall maximum gain of 89 dB and a noise figure of 3.8 dB. Phase and amplitude mismatches of the demodulator are below 10 and 0.1 dB, respectively. The high linearity required by the blocking and intermodulating signals, which are not completely suppressed by the IF filter, has been achieved using 4.7 mA from the 2,5-V power supply. View full abstract»

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  • CMOS switched-op-amp-based sample-and-hold circuit

    Publication Year: 2000 , Page(s): 109 - 113
    Cited by:  Papers (23)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (122 KB)  

    This paper presents a sample-and-hold design that is based on a switched-op-amp topology. Charge injection errors are greatly reduced by turning off transistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feed through error is mostly signal-independent and is cancelled out by a pseudodifferential topology. Switched-opamps are designed and fabricated in a 2-/spl mu/ CMOS technology. The measurement results show that the harmonics are at least 78 dB below the signal level. Both the measurement results from fabricated ICs and simulation results suggest the potential benefits of this approach in comparison to traditional switched-capacitor circuits. View full abstract»

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  • Single-ended SRAM with high test coverage and short test time

    Publication Year: 2000 , Page(s): 114 - 118
    Cited by:  Papers (10)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (115 KB)  

    The advantages of low power dissipation and smaller chip area for single-ended SRAMs are well known. In this paper, we present the configuration and test strategy of a single-ended, six-transistor SRAM. The benefits of short test time, no retention test, and high test coverage are verified. The goals of low power, high quality control, and short test time of the full CMOS SRAM can be achieved. View full abstract»

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  • Low-power embedded SRAM with the current-mode write technique

    Publication Year: 2000 , Page(s): 119 - 124
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB)  

    In the traditional current-mode SRAMs, only the read operation is performed in the current mode. In this paper, we propose to use the current-mode technique in both the read and write operations. Due to the current mode operation, voltage swings at bit lines and data lines are kept very small during both read and write. Then, the ac power dissipation of bit lines and data lines, which is proportional to the voltage swing, can be significantly saved. A new current-mode 128/spl times/8 SRAM has been designed based on a 0.6 /spl mu/m CMOS technology, and the new SRAM consumes only 30% of the power of an SRAM with current-mode read but voltage mode write operations. Besides a test chip for the new SRAM, it has also been embedded in an 8-bit 1.1-controller. Experimental results show good agreement with the simulation results and prove the feasibility of the new technique. View full abstract»

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  • A scannable pulse-to-static conversion register array for self-timed circuits

    Publication Year: 2000 , Page(s): 125 - 128
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (46 KB)  

    This paper describes the design and hardware results of a scannable pulse-to-static conversion register array for self-timed circuits. The circuits include a self-timed control circuit and a 64-bit register array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control block allows it to require only one system clock input. The evaluation, reset, and write-enable controls are all generated within the control macro. The register array is a level-sensitive scan design, which is compatible and complies with SRCMOS test modes. This type of register array can facilitate the synchronous/asynchronous interfaces, pipelined operation, power management, and testing of advanced digital systems employing a mixture of static and dynamic circuits to achieve low power and high performance. View full abstract»

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  • Corrections to "a high-swing CMOS telescopic operational amplifier"

    Publication Year: 2000 , Page(s): 129
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (40 KB)  

    First Page of the Article
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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan