# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

## Filter Results

Displaying Results 1 - 12 of 12
• ### On computing the sizes of detected delay faults

Publication Year: 1990, Page(s):299 - 312
Cited by:  Papers (71)
| | PDF (1192 KB)

Defects in integrated circuits can cause delay faults of various sizes. Testing for delay faults has the goal of detecting a large fraction of these faults for a wide range of fault sizes. Hence, an evaluation scheme for a delay fault test must not only compute whether or not a delay fault was detected, but also calculate the sizes of detected delay faults. Delay faults have the counterintuitive p... View full abstract»

• ### Scaling theory for fault stealing algorithms in large systolic arrays

Publication Year: 1990, Page(s):290 - 298
Cited by:  Papers (4)
| | PDF (624 KB)

The performance of fault-stealing algorithms for very large, multipipeline systolic arrays is considered. Extensions of an existing algorithm are proposed, and with these extensions the algorithm is shown to work for large array sizes. Using the modified algorithms as a testbed, a scaling theory that predicts, on the basis of performance for a single small array, the performance of the algorithm f... View full abstract»

• ### Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation

Publication Year: 1990, Page(s):236 - 247
Cited by:  Papers (49)  |  Patents (2)
| | PDF (992 KB)

Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined t... View full abstract»

• ### Adaptive meshing schemes for simulating dopant diffusion

Publication Year: 1990, Page(s):276 - 289
Cited by:  Papers (9)  |  Patents (5)
| | PDF (1132 KB)

Two adaptive meshing schemes for the efficient simulation of dopant diffusion in silicon using the finite element method are presented. The first scheme is based on an adaptation criterion which is obtained by computing a local error estimate derived from the finite element solution itself. The second scheme is based on a mesh adaption criterion which uses physical diffusion parameters. A comparis... View full abstract»

• ### An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations

Publication Year: 1990, Page(s):225 - 235
Cited by:  Papers (53)  |  Patents (5)
| | PDF (832 KB)

One of the excitations, carrier', is a large signal and an arbitrary T-periodic function of time. The other excitation, signal', is considered as a small perturbation to the periodic steady-state response driven by the carrier. To find a small signal frequency response for the `signal', the method uses variational equations around the periodic steady-state response. These linearized tim... View full abstract»

• ### Two-dimensional IC layout compaction based on topological design rule checking

Publication Year: 1990, Page(s):260 - 275
Cited by:  Papers (5)  |  Patents (5)
| | PDF (1588 KB)

An effective approach to two-dimensional compaction of VLSI circuit layouts is discussed. Active devices are described in terms of circular primitives called bubbles. The wires are treated topologically in that no geometric representation is used for them during compaction. This avoids expensive geometrical manipulations of the wires. Cells are compacted by moving bubbles one at a time along desig... View full abstract»

• ### A parallel branch and bound algorithm for test generation

Publication Year: 1990, Page(s):313 - 322
Cited by:  Papers (53)
| | PDF (940 KB)

For circuits of VLSI complexity, test generation time can be prohibitive. Most of the time is consumed by hard-to-detect (HTD) faults, which might remain undetected even after a large number of backtracks. The problems inherent in a uniprocessor implementation of a test generation algorithm are identified, and a parallel test generation method which tries to achieve a high fault coverage for HTD f... View full abstract»

• ### Multiple storage adaptive multi-trees

Publication Year: 1990, Page(s):248 - 252
Cited by:  Papers (4)
| | PDF (440 KB)

A powerful technique (multiple storage multi-trees) for storage of geometrical data in CAD applications is presented. A significant improvement has been obtained in the field of region query performance. Memory requirements are slightly lower than for R.L. Brown's well-known multiple storage quadtrees (ibid., vol.5, no.3, p.413-9, 1986). Experimental results for the new data structure are presente... View full abstract»

• ### New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement

Publication Year: 1990, Page(s):323 - 328
Cited by:  Papers (55)  |  Patents (3)
| | PDF (524 KB)

Two approaches for the repair of large random access memory (RAM) devices in which redundant rows and columns are added as spares are presented. These devices, referred to as redundant RAMs, are repaired to achieve acceptable yield at manufacturing and production times. The first approach, the faulty line covering technique, is a refinement of the fault-driven approach. This approach finds the opt... View full abstract»

• ### Temperature measurement and equilibrium dynamics of simulated annealing placements

Publication Year: 1990, Page(s):253 - 259
Cited by:  Papers (24)  |  Patents (2)
| | PDF (572 KB)

One way to alleviate the heavy computation required by simulated annealing placement algorithms is to replace a significant fraction of the higher or middle temperatures with a faster heuristic, and then follow it with simulated annealing. A crucial issue in this approach is the determination of the starting temperature for the simulated annealing phase-a temperature should be chosen that causes a... View full abstract»

• ### Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits

Publication Year: 1990, Page(s):329 - 331
Cited by:  Papers (14)
| | PDF (284 KB)

A sequence of input vectors which detects all transistor stuck-open faults in a CMOS combinational circuit is a complete test sequence. Given a complete set of two-pattern tests for transistor stuck-open faults in a CMOS circuit, it is shown that a complete test sequence of minimum length can be obtained efficiently. A precise description of this problem and examples to illustrate the method are p... View full abstract»

• ### Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits

Publication Year: 1990, Page(s):332 - 336
Cited by:  Papers (20)  |  Patents (1)
| | PDF (544 KB)

The totally self-checking (TSC) concept is well established for applications in the area of online error-indication. TSC circuits can detect both transient and permanent faults. They consist of a functional circuit with encoded inputs and outputs and a checker which monitors these outputs. The TSC concept can be generalized for the functional circuits using the strongly fault-secure (SFS) concept.... View full abstract»

## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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## Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu