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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 2 • Date Feb 1990

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Displaying Results 1 - 12 of 12
  • Techniques for calculating currents and voltages in VLSI power supply networks

    Publication Year: 1990, Page(s):126 - 132
    Cited by:  Papers (24)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    Analysis of power distribution in VLSI circuits requires the solution of a large network of resistors and current sources. Fortunately, these resistor networks have certain characteristic properties that permit partitioning into smaller, easier to solve sections. The authors present a set of techniques that can be used to identify and quickly solve three characteristic network configurations: tree... View full abstract»

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  • OPASYN: a compiler for CMOS operational amplifiers

    Publication Year: 1990, Page(s):113 - 125
    Cited by:  Papers (207)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1140 KB)

    A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit top... View full abstract»

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  • A linear-time algorithm for routing in a convex grid

    Publication Year: 1990, Page(s):180 - 184
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    An algorithm for the problem of routing two-terminal nets in a convex grid is presented. A convex grid is a subset R of the planar rectangular grid without any nontrivial holes, i.e. every finite face has exactly four incident vertices, so that every vertical and horizontal line crosses the boundary of the grid at most twice. A net is a pair of vertices of nonmaximal degree on the boundar... View full abstract»

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  • A method of fault simulation based on stem regions

    Publication Year: 1990, Page(s):212 - 220
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    An exact fault simulation can be achieved by simulating only the faults on reconvergent fan-out stems, while determining the detectability of faults on other lines by critical path tracing within fan-out-free regions. The authors have delimited, for every reconvergent fan-out stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such ... View full abstract»

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  • `Zone-refining' techniques for IC layout compaction

    Publication Year: 1990, Page(s):167 - 179
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1324 KB)

    Zone-refining refers to a technique that forms a basis for layout compaction algorithms intermediate between one-dimensional (1-D) compactors and two-dimensional (2-D) placement techniques. An expanded zone in which 2-D refinement techniques are employed is repeatedly swept across the layout in different directions. The basic principle is reviewed and the computational complexity of zone refining ... View full abstract»

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  • Hybrid routing

    Publication Year: 1990, Page(s):151 - 157
    Cited by:  Papers (21)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    A general-purpose routing algorithm for very-large-scale integrated (VLSI) circuits and printed circuit board (PCB) designs is proposed. Ideas behind the maze-running algorithm and the hierarchical routing algorithm are combined into a powerful algorithm called hybrid routing. The new algorithm demonstrates a speed compatible to a hierarchical router and produces routings with quality equivalent t... View full abstract»

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  • Design for test using partial parallel scan

    Publication Year: 1990, Page(s):203 - 211
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1012 KB)

    Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the drawback that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. A scan design technique termed partial parallel scan which reduces test application effort by one t... View full abstract»

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  • Logic simulation with current-limited switches

    Publication Year: 1990, Page(s):133 - 141
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoff's laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is ea... View full abstract»

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  • New algorithms for the rectilinear Steiner tree problem

    Publication Year: 1990, Page(s):185 - 193
    Cited by:  Papers (62)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    An approach to constructing the rectilinear Steiner tree (RST) of a given set of points in the plane, starting from a minimum spanning tree (MST), is discussed. The main idea in this approach is to find layouts for the edges of the MST that maximize the overlaps between the layouts, thus minimizing the cost (i.e. wire length) of the resulting rectilinear Steiner tree. Two algorithms for constructi... View full abstract»

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  • A faster compaction algorithm with automatic jog insertion

    Publication Year: 1990, Page(s):158 - 166
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    The work of F.M. Maley (Proc. Chapel Hill Conf. on VLSI, p.261-83, 1985) on one-dimensional compaction with automatic jog insertion is refined. More precisely, an algorithm with running time O((n2+k)log n), where k=O(n3) is a quantity which measures the difference between the input and output sketch, is given, and... View full abstract»

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  • Table-based modeling of delta-sigma modulators using ZSIM

    Publication Year: 1990, Page(s):142 - 150
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    ZSIM, a nonlinear Z-domain simulator for sampled-data systems, is presented and verified. ZSIM integrates analytic tools, a difference equation simulator, a table-based nonlinear Z-domain simulator, and digital signal processing into a workstation environment to provide fast and accurate simulation of delta-sigma modulators. The use of table-based simulation allows simulation of ... View full abstract»

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  • Completely automatic completion of VLSI designs

    Publication Year: 1990, Page(s):194 - 202
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    Most VLSI designs consist of a number of blocks, like RAMs, ROMs, data paths, and random logic, which ultimately must be integrated. Methods for performing this integration have generally required manual intervention, such as the iterative operation of placement programs and routing programs. Here, the term fusion is introduced to denote any automatic method which performs that integration complet... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu