IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • Jan 1988

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Displaying Results 1 - 15 of 15
  • SOCRATES: a highly efficient automatic test pattern generation system

    Publication Year: 1988, Page(s):126 - 137
    Cited by:  Papers (362)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1076 KB)

    An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techn... View full abstract»

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  • Concurrent error correction in systolic architectures

    Publication Year: 1988, Page(s):117 - 125
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    It is shown how two features of systolic arrays in which the cells retain partial results rather than pass them on can be used to facilitate testing and fault localization with no modification of the systolic design; the monitoring is performed either by software in the host processor or by hardware following the system output. One feature is the ability to enter identical sequences of inputs into... View full abstract»

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  • Testing for multiple faults in domino-CMOS logic circuits

    Publication Year: 1988, Page(s):109 - 116
    Cited by:  Papers (32)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to initialize the domino-CMOS circuit and apply a multiple stuck-at fault test set based on the gate-l... View full abstract»

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  • A design of programmable logic arrays with random pattern-testability

    Publication Year: 1988, Page(s):5 - 10
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is introduced. Low area overhead is achieved by adding a mask array between the input-decoder and the AND array of the PLA. Several variations of the proposed approach are presented. The probability of fault detection and the test length are examined for both stuck-type and crosspoint-type fault... View full abstract»

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  • Multiple fault detection using single fault test sets

    Publication Year: 1988, Page(s):100 - 108
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    A simulation study of the 74LS181 4-b ALU (arithmetic logic unit) using 16 complete single stuck-at fault test sets demonstrated significantly higher multiple stuck-at fault coverage than predicted by previous theoretical studies. Analysis of the undetected multiple faults shows the effect of circuit and test set characteristics on fault coverage. A fault masking property, defined as self-masking,... View full abstract»

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  • Hybrid designs generating maximum-length sequences

    Publication Year: 1988, Page(s):91 - 99
    Cited by:  Papers (53)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    Two hybrid schemes for the design of maximum-length sequence generators (MLSGs) are presented. Compared to an n-stage maximum-length LFSR (for generating 2n-1 nonzero distinct states) that uses m exclusive-or (XOR) gates, this hybrid MLSG will use exactly (m+1)/2 XOR gates if its characteristic polynomial meets certain requirements. For applications such as ex... View full abstract»

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  • Probability models for pseudorandom test sequences

    Publication Year: 1988, Page(s):68 - 74
    Cited by:  Papers (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    A probabilistic model for pseudorandom testing of combinational circuits is presented. The expected fault coverage is shown to be accurately approximated as a series of exponentials that depends on the test length and the fault detectabilities. The derivations do not require the pattern generator to have the same number of stages as there are network inputs View full abstract»

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  • Logic design verification via test generation

    Publication Year: 1988, Page(s):138 - 148
    Cited by:  Papers (131)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test patterns that were developed to detect single stuck-line faults in the gate-level implementation are used instead to compare the gate-level implementation with the functional-level specification. In the presence of certain hy... View full abstract»

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  • Methodologies for testing embedded content addressable memories

    Publication Year: 1988, Page(s):11 - 20
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    A design strategy is presented for efficient and comprehensive testing when the address, data, and bit lines are not externally controllable or observable. Three algorithms are developed for testing common functional faults in content-addressable memories. One provides a novel method for detecting pattern-sensitive faults over a neighborhood size of nine and thereby tests a w-word content... View full abstract»

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  • Bounds and analysis of aliasing errors in linear feedback shift registers

    Publication Year: 1988, Page(s):75 - 83
    Cited by:  Papers (84)  |  Patents (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Aliasing errors in linear feedback shift registers (LFSRs) used as signature analysis registers in self-testing networks are considered. A bound on aliasing is established by a straightforward algebraic analysis of LFSRs. It is calculated as a function of p, the probability of an error occurring at an output of the network under test. This bound is robust but is only good for p c... View full abstract»

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  • The design of concurrent error diagnosable systolic arrays for band matrix multiplications

    Publication Year: 1988, Page(s):21 - 37
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1020 KB)

    The characteristics of a systolic array and the important issues in fault-tolerant systolic computing are presented. Recent efforts to optimize the performance of a band matrix multiplication systolic array (BMMSA) is discussed, concentrating on the fundamental differences between the Kung-Leiserson and Huang-Abraham schemes of systolic design in order to exemplify the extremes in design philosoph... View full abstract»

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  • Analysis and proposal of signature circuits for LSI testing

    Publication Year: 1988, Page(s):84 - 90
    Cited by:  Papers (26)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    A novel signature analysis method for LSI testing using multiple-input signature registers (MISRs) is presented. First, the double-bit and triple-bit error-detecting probabilities are analyzed theoretically in the case in which a single MISR defined by a primitive polynomial is used for a signature circuit. Second, to enhance the capability of detecting multiple errors contained in testing pattern... View full abstract»

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  • TRIM: testability range by ignoring the memory

    Publication Year: 1988, Page(s):38 - 49
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    The testability by random test patterns of faults in the logic surrounding embedded RAMs is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM View full abstract»

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  • Design of large embedded CMOS PLAs for built-in self-test

    Publication Year: 1988, Page(s):50 - 59
    Cited by:  Papers (17)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    A novel scheme to design built-in self-test programmable logic arrays (PLAs) implemented with CMOS technology is described, which is attractive for large arrays. These PLAs can perform function-independent self-test at normal operating speed, can detect CMOS switch-level faults, and have a lower area overhead than any other BIST scheme. A sequential parity checking technique is used to test for th... View full abstract»

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  • A new approach to the design of built-in self-testing PLAs for high fault coverage

    Publication Year: 1988, Page(s):60 - 67
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    Four critical requirements are identified for the built-in self-testing of programmable logic arrays (BIST PLAs): the test set to test the PLA as well as the output response must be independent of the function of the PLA; the test pattern generator (TPG) and the response evaluator circuits must be simple to keep the extra logic overhead to a minimum; the fault coverage of the PLA must be within ac... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu