By Topic

Electronics Packaging Manufacturing, IEEE Transactions on

Issue 4 • Date Oct. 1999

Filter Results

Displaying Results 1 - 17 of 17
  • Abstracts

    Page(s): 249 - 252
    Save to Project icon | Request Permissions | PDF file iconPDF (36 KB)  
    Freely Available from IEEE
  • Author index

    Page(s): 340 - 342
    Save to Project icon | Request Permissions | PDF file iconPDF (183 KB)  
    Freely Available from IEEE
  • Subject index

    Page(s): 342 - 347
    Save to Project icon | Request Permissions | PDF file iconPDF (160 KB)  
    Freely Available from IEEE
  • Recent advances in the development of no-flow underfill encapsulants-a practical approach towards the actual manufacturing application

    Page(s): 331 - 339
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    No-flow underfill technology has been proven to have potential advantages over the conventional underfill technology, and a no-flow underfill material (called G25) has been developed and reported in our prior papers. In this paper, two modified no-flow underfill materials are studied. Compared to the G25 no-flow underfill material, these two materials can be fully post-cured at the temperature below 170°C. These two materials also exhibit lower coefficient of thermal expansion (CTE), lower moisture absorption, better adhesion, and more fluxing stability. In this study, a differential scanning calorimetry (DSC) is used to study the curing kinetics and glass transition temperature (DSC Tg) of the two materials. Thermo-mechanical analyzer (TMA) is used to investigate the heat distortion temperature (TMA Tg) and the coefficient of thermal expansion (CTE). Dynamic-mechanical analyzer (DMA) is used to measure the storage modulus (E') and loss modulus (E") within the temperature range from 25°C to 250°C and then estimate the cross-linking density (p) of the cured material system. Rheometer is used to investigate the material viscosity. Die shear testing is conducted to investigate the adhesive strength between the cured underfill material and polyimide passivation layer. Surface mount technology (SMT) reflow oven, quartz chips and copper laminated FR4 substrates are used to in-situ test the processability of the two materials. Scanning electron microscopy (SEM) is used to observe the integrity of the reflowed solder interconnects. A potential approach toward the production application of no-flow underfill material is then proposed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling ceramic filled polymer integrated capacitor formation using neural networks

    Page(s): 314 - 318
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    Integrated decoupling capacitors for MCM-L/D technology are an important component for next-generation electronic packaging applications. This paper presents a statistically designed experiment for systematic characterization of the dielectric constant and loss tangent of integrated capacitors formed by mixing lead magnesium niobate (PMN) particles into polyimide and benzocyclobutene (BCB) polymer dielectric layers. We determine these quantities as a function of the type of polymer material, a volume fraction of ceramic in the polymer matrix, a polymer cure time, and polymer cure temperature. These factors have been examined by means of a D-optimal experiment. Results indicate manipulation of each of the four factors over the ranges examined lead to considerable variation in dielectric constant and loss tangent. Based on data from these experiments, we train neural networks to model this process variation as a function of above variables. Using this methodology, we determine proper combinations of polymer/ceramic materials and processing conditions to achieve desirable electrical properties View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Characterization of underfill/substrate interfacial toughness enhancement by silane additives

    Page(s): 264 - 267
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    This work experimentally measures the apparent fracture toughness of the interfaces between epoxy-based underfill materials and various substrates including aluminum, polyimide, BCB, and printed wiring boards (FR-4) with solder mask. A small amount of silane coupling agent is added to the base underfill in order to form various underfill derivatives, and double layer specimens with preexisting interfacial cracks are prepared for four-point bending tests. The measurements are qualitatively correlated to each silane additive. The purpose of adding silane additives was to enhance the adhesion; the enhancement of interfacial toughness was found to strongly depend on the type of substrate. The results of this study have important implications in flip-chip reliability where interfacial cracking is one of the major failure modes View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of Ag particle size on electrical conductivity of isotropically conductive adhesives

    Page(s): 299 - 302
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    The present work is to introduce nanoparticles in micro-sized metal particles to study particle distribution in polymer matrix. Previous examinations of the silver-filled particles reveal that the micro-sized particle fillers appear as full density silver flakes, while nanoparticle fillers appear as highly porous agglomerates, similar to open-cell foams. Actually little work has been carried out to study the cross-sectional area of a particle-particle-contact in isotropically conductive adhesives (ICA). In this study, transmission electron microscope is chosen as a main measure to analyze the distribution of different-sized particles. The percentage of the nanoparticles varies from 20 wt% and 50 wt% to full percentage within micro-sized particles, and the total metal content in epoxy resin is 70 wt%. So the change of contact area and contact behavior with various volume ratio of nano-sized and micro-sized particles was investigated. At the same time, the electrical resistivity was measured, which is compared with the different level of the filler loading View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Study on the relationship between the surface composition of copper pads and no-flow underfill fluxing capability

    Page(s): 268 - 273
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    The purpose of this paper is to investigate the effect of copper pad surface composition on the wetting of solder bumps during reflow process for a certain no-flow underfill material. A purchased copper foil which is laminated on FR4 board is used as a control surface. Six different procedures are followed to prepare the surface of the copper foil with six different compositions. XPS is then used to analyze the surface compositions of the six surfaces and the control surface. An in-house developed G25 no-flow underfill encapsulant is used to examine the wetting status of eutectic solder balls on these copper surfaces. The correlation of the copper surface compositions with the solder wetting is then established. It is verified that the compositions of the copper foil surfaces strongly depend on the cleaning procedures. For G25 no-flow underfill material, copper oxide (CuO) is the main composition that prevents the solder ball from wetting the copper foils while the observed organic contamination does not have noticeable effect on the solder wetting View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-temperature, low-modulus adhesive attach for large-area thin-film processing on silicon and alumina tiles

    Page(s): 290 - 294
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    The fabrication of high-density interconnect structures typically involves sequential processing of alternate layers of thin organic dielectric materials and conducting copper lines. With the continued push toward low-cost fabrication, large-area processing of thin-film materials is being aggressively pursued by the electronic packaging industry. The objective of the ongoing work at Georgia Tech is to develop innovative materials, models, and processing techniques to facilitate large-area processing of alumina and silicon tiles. As the alumina and silicon tiles are commercially available in smaller dimensions, a palletization approach has been developed to facilitate large-area processing. In the palletization approach, alumina and silicon tiles are attached to re-usable glass pallets with an in-house developed thermally-stable, reworkable, and highly-compliant adhesive View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Smart tooling for assembly of thin flexible systems

    Page(s): 308 - 313
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    Emerging electronic assemblies are demanding lower cost, lighter weight, miniaturized packages mounted on thin flexible circuit boards and/or flex circuits. However, the compliant nature of the flex substrates poses new processing technology challenges for standard surface mount assembly equipment. A particular challenge is fixture tooling. The flexible substrate experiences significant transverse displacements under perpendicular assembly and/or fixturing forces during solder paste printing and component placement processes. The transverse displacements result in misregistration of the component leads and substrate bond pads, leading to severe assembly process defects. The solder reflow process further complicates the issue due to the thermo-mechanical warpage induced. Conventional assembly equipment utilizes dedicated tooling designed to handle rigid circuit board assemblies. As electronic assemblies move toward very fine pitch surface mount packages, chip scale packages, and flip chip attachment assembled to thin flexible double-sided circuit boards, reengineered and specialized dedicated tooling for fixturing flexible substrates in standard assembly equipment are becoming extremely important. This paper focuses on developing analysis methodologies and theories for implementing machine dedicated Smart Tooling. The primary goals being to determine the impact of fixturing on assembly process quality and to determine optimum fixturing configurations for thin flexible circuit board assemblies based on circuit design data. A mathematical model to describe both transverse and perpendicular displacements of flex substrates is developed, and its closed form solution for transverse displacements is obtained. Fixturing configurations based on a perimeter support technique of flex substrates is analyzed to minimize transverse displacements View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High performance conductive adhesives

    Page(s): 324 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    Isotropic conductive adhesives (ICAs) have been developed as an alternative for traditional tin/lead (Sn/Pb) solders for electronic applications. Compared to mature soldering technology, conductive adhesive technology is still in its infant stage, therefore, there are some limitations for current commercial ICAs. Two critical limitations are poor impact performance and unstable contact resistance with nonnoble metal finished components. These limitations seriously hindered the wide applications of ICA's. No current commercial ICAs show both desirable impact performance and stable contact resistance. In this paper, novel conductive adhesives were formulated using mixtures of an epoxide-modified polyurethane resin and a bisphenol-F type epoxy resin and a corrosion inhibitor. Cure profiles, rheology, and dynamic mechanical properties of the conductive adhesives were studied using a differential scanning calorimeter (DSC), a rheometer, and a dynamic mechanical analyzer (DMA), respectively. Impact strength and contact resistance with several nonnoble metals (Sn/Pb, Sn, and copper) of these conductive adhesives were tested and compared to those of a commercial conductive adhesive. It was found that these in-house conductive adhesives showed superior impact performance and substantially stable contact resistance with nonnoble metal finished components during elevated temperature and humidity aging View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sources and control of volatile gases hazardous to hermetic electronic enclosures

    Page(s): 319 - 323
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    Four gases that threaten operating reliability may be present in hermetic electronic enclosures. Condensates of moisture and/or ammonia can cause metallization corrosion. Hydrogen is a rapid diffuser that can degrade metal-oxide-semiconductor (MOS) device operation. Oxygen can cause oxidation and ensuing failure of solder attachment materials within the sealed package. Other gases, such as carbon dioxide, helium, argon, and organic volatiles are not threats to reliability, but do provide clues to package materials behavior. Knowing sealed package ambient gas composition helps improve materials and processes for hermetic sealing and enables process control to assure reliable products. This paper describes the analysis method for hermetic microelectronics, residual gas analysis (RGA), available at only a few laboratories worldwide. It discusses sealing processes and package piece part materials that are sources of volatiles hazardous to product reliability. It presents materials selection and improvement considerations to reduce and control dangerous volatiles in hermetic packages View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Studies of latent catalyst systems for pot-life enhancement of flip chip underfills

    Page(s): 282 - 289
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    Underfill encapsulant is the material used in flip-chip devices that fills the gap between the integrated circuit (IC) chip and the organic board, and encapsulates the solder interconnects. This underfill material can dramatically enhance the reliability of flip-chip devices as compared to nonunderfilled devices. Current underfill encapsulants generally consist of epoxy resin, anhydride hardener, catalyst, silica filler, and other additives to enhance the adhesion, flow, etc. Catalyst determines underfill properties including pot-life, cure speed, and cure temperature. However, long pot-life and fast cure at relatively low temperature (~150°C) are desirable, as such, it requires a room temperature latent catalyst which would be able to catalyze the epoxy curing efficiently at desirable temperature. Currently, the pot-life of commercial underfills at room temperature is normally less than one day. The underfills have to be stored in the freezer at -40°C and in the dry ice for shipping. The objective of this work was to test various catalyst systems that have the potential to enhance the pot-life of the underfill without adversely affecting its curing. The pot-lives of the underfill with various catalysts were obtained from their viscosity versus time relationships, which were established by measuring the viscosities of the underfill with these catalysts periodically using a stress-controlled rheometer. The curing of the underfills was studied using a differential scanning calorimetry (DSC). The pot-life and curing data of the underfill pre-mixed with each of these catalysts are presented in this paper View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Initial investigations into low-cost ultra-fine pitch solder printing process based on innovative laser printing technology

    Page(s): 303 - 307
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    Advances in electronics packaging and assembly technology are driving increased demand for ultra-fine pitch solder deposition. In this work, innovative solder deposition techniques based on laser printing are investigated for low-cost ultra-fine pitch printing applications. This paper investigates the feasibility of using solder particles in off-the-shelf xerographic technology. The physics of two development systems (dual component and monocomponent) is discussed. This inquisition leads to a discussion of triboelectric charging of the solder toners, coating the solder with thin dielectrics, and charge induction by an applied electric field. This initial investigation explores the basic feasibility of xerographic printing techniques using solder and defines future work View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of the wafer level compressive-flow underfill process and its involved materials

    Page(s): 274 - 281
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    This paper describes a wafer level compressive-flow underfill process for a novel SMT transparent flip-chip technology. In this flip-chip technology, a liquid fluxable wafer level compressive-flow underfill (WLCFU) material is first coated on the active side of an entire patterned and bumped wafer. The WLCFU layer is dried at an elevated temperature to form a solid layer. The coated bumped wafer is then diced into individual chips, which are then placed on a carrier film with their active side to the tacky side of the carrier film. These diced individual chips are then picked from the tacky carrier film and placed on a substrate such as a PWB board using standard SMT equipment. At an elevated temperature (100-180°C) during solder reflow, the solid WLCFU layer can be re-melted and can easily fill in the gaps between chip and substrate. After solder reflow (190-200°C), the WLCFU material can be fully cured. A B-stage epoxy technology is used to develop this WLCFU material and the tacky material on the carrier film. A properly selected fluxing agent is added to both the WLCFU and the tacky materials to provide sufficient fluxing capability for good solder interconnection. A thermo-gravimetrical analyzer (TGA) is used to investigate the drying kinetics and the material weight loss during the reflow process. Differential Scanning Calorimetry (DSC) is used to study the curing kinetics of the prepared formulations. A thermo-mechanical analyzer (TMA) is used to investigate the heat distortion temperature (TMA Tg) and the coefficient of thermal expansion (CTE). A dynamic-mechanical analyzer (DMA) is used to measure the storage modulus (E') and cross-linking density (ρ) of the cured materials. A rheometer is used to investigate viscosity (η) change with the temperature increase during the solder reflow process. Preliminary results demonstrate the feasibility of the proposed novel flip-chip technology with the developed WLCFU and tacky materials. The basic qualifications of the WLCFU material are examined. Some technical barriers related to this technology are also discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Separation of low molecular siloxanes for electronic application by liquid-liquid extraction

    Page(s): 295 - 298
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB)  

    Silicone resins are widely used for electronic packaging as potting and encapsulating materials. Silicone resins have many advantages for electronic packaging applications such as superior electrical properties, thermal stability, low water absorption, etc. Furthermore, silicone resins are not only used as protective materials for integrated circuit (IC) devices but also as conducting materials for interconnection. However, silicone resins have two big drawbacks: low adhesion strength and low molecular weight creep. A simple liquid-liquid extraction method has been developed to purify silicone resins, which will improve adhesion strength and eliminate low molecular weight creep. This paper describes the results of the liquid-liquid extraction method to remove low molecular weight cyclic siloxanes. Fourier transform-infrared (FT-lR) spectroscopy was used to monitor the removal rate of low molecular weight cyclic siloxanes. Thermogravimetric analysis (TGA) was used to evaluate the purity of silicone resin. Gas chromatography-mass spectrometry (GC/MS) was used to identify the low molecular weight cyclic siloxanes. Thermomechanical analyzer (TMA), dynamic mechanical analyzer (DMA), and die shear test were used for evaluate the properties of silicone resin View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Do chip size limits exist for DCA?

    Page(s): 255 - 263
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University