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IEEE Micro

Issue 1 • Date Feb. 1990

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Displaying Results 1 - 8 of 8
  • Implementing Sparc in ECL

    Publication Year: 1990, Page(s):10 - 22
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1350 KB)

    A joint development project that implemented Sun Microsystems' scalable processor architecture (Sparc) with Bipolar Integrated Technology's bipolar emitter-coupled logic (ECL) is described. The authors review both ECL technology and the features of BIT's ECL technique and discuss how board and cache considerations influenced the chip designs. Also discussed are the integer unit pipeline, system in... View full abstract»

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  • Hot chips and soggy software

    Publication Year: 1990, Page(s):23 - 26
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB)

    The author discusses the bottlenecks that impair performance of a computer system and discusses the success of the RISC (reduced-instruction-set computer) approach. He attributes it, at least in part, to the fact that all the seminal work on the RISC chips was carried out in close conjunction with a strong compiler team. He discusses issues that designers of computer systems must consider and exam... View full abstract»

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  • The i486 CPU: executing instructions in one clock cycle

    Publication Year: 1990, Page(s):27 - 36
    Cited by:  Papers (9)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (957 KB)

    The author discusses the design goals of the i486 development program, which were to ensure binary compatibility with the 386 microprocessor and the 387 math coprocessor, increase performance by two to three times over a 386/387 processor system at the same clock rate, and extend the IBM PC standard architecture of the 386 CPU with features suitable for minicomputers. A cache integrated into the i... View full abstract»

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  • Compiler challenges with RISCs

    Publication Year: 1990, Page(s):37 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    It is argued that despite the simplified instruction sets of reduced instruction-set computers (RISCs), designing their compilers is not so simple. This viewpoint is substantiated by considering a subproblem that arises in designing a calling sequence, namely, how to pass arguments to a procedure. A constraint of the solution is that the ubiquitous print function printf (from the C programming lan... View full abstract»

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  • Developing the GX graphics accelerator architecture

    Publication Year: 1990, Page(s):44 - 54
    Cited by:  Papers (3)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (945 KB)

    A novel approach to acceleration is described whereby high-level graphics on entry-level workstations has become practical. In the GX, the host CPU functions as the intelligent controller and two large ASICs (application-specific ICs) supply hardwired graphics functions. An arbitrary quadrilateral is the GX's only geometric primitive. However, it can readily approximate circle and arc primitives w... View full abstract»

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  • Developing the WTL3170/3171 Sparc floating-point coprocessors

    Publication Year: 1990, Page(s):55 - 64
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (734 KB)

    The development of the first two members in a family of scalable-processor-architecture (Sparc)-compatible parts is described. With varying frequency and latency performance, the chips work with the first two integer unit (IU) implementations from other Sparc vendors. These are the first Sparc chips to integrate all floating-point controller functions, floating-point register files, and 64-b ALU (... View full abstract»

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  • The 68040 processor. I. Design and implementation

    Publication Year: 1990, Page(s):66 - 78
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1258 KB)

    The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controller... View full abstract»

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  • Appropriate and inappropriate legal protection of user interfaces and screen displays. V. How different forms of copyright protection interact with policy

    Publication Year: 1990, Page(s):79 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    For pt.IV see ibid., vol.9, no.6, p.84 (1989). The author considers which proposed regime of copyright protection for screen displays best serves the public policy requirements discussed earlier. Those requirements center on encouraging progress in the software field by providing incentives to innovators and investors while preserving the availability of utilitarian screen display techniques to ot... View full abstract»

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School of Electrical and Computer Engineering
IBM T.J. Watson Research Center