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Components and Packaging Technologies, IEEE Transactions on

Issue 4 • Date Dec. 1999

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Displaying Results 1 - 18 of 18
  • Foreword contributions from the 1998 intersociety conference on thermal and thermomechanical phenomena in electronic packages

    Publication Year: 1999 , Page(s): 481 - 483
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  • Author index

    Publication Year: 1999 , Page(s): 597 - 600
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    Freely Available from IEEE
  • Subect index

    Publication Year: 1999 , Page(s): 600 - 609
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  • Transient thermal management of temperature fluctuations during time varying workloads on portable electronics

    Publication Year: 1999 , Page(s): 541 - 550
    Cited by:  Papers (26)
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    This paper describes the investigation of solid to liquid phase change materials (PCM's) for passive energy storage during the condition of time varying workloads on portable electronics. The model investigated includes a thermal control unit (TCU) embedded in an epoxy polymer. A TCU is an enclosure that contains phase change material (PCM) and a thermal conductivity enhancer, is located near the power source, and acts as an energy storage and heat-spreading module. Physical experiments were carried out to investigate the performance improvements of introducing a TCU into an embedded system and were used to validate the accuracy of the numerical model. Numerical simulations were performed to study the effect duty cycles and substrate thermal conductivities have on the thermal performance of the electronic wearable computer system with passive energy storage. Additionally, the TCU was numerically modeled to determine the influence of boundary conditions on TCU performance. To quantify the improvements of the system, metrics were developed from analyzing the thermal evolution of the TCU parameters, such as temperature fields, temperature bands, PCM characteristics, and power loads. Results indicate that using a TCU for passive energy storage significantly increases the portable electronics system's operational performance. Duty cycles with the same average power over the duration of the cycle do not influence the length of the PCM phase change time, but do impact the mean value of the temperature fluctuation bands View full abstract»

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  • Microwave model of anisotropic conductive film flip-chip interconnections for high frequency applications

    Publication Year: 1999 , Page(s): 575 - 581
    Cited by:  Papers (18)
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    Microwave model and high-frequency measurement of the anisotropically conductive film (ACF) flip-chip interconnection was investigated using a microwave network analysis. The test integrated circuits (ICs) were fabricated using a 1-poly and 3-metal 0.6 μm Si process with an inverted embedded microstrip structure. As flip chip bumps, electroless Ni/Au plating was performed on Al input/output (I/O) pads of test IC chips, As an interconnect material, several ACFs were prepared and flip-chip bonded onto the Rogers(R) RO4003 high frequency organic substrate. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe, and the cascade transmission matrix conversion was performed. The same measurements and conversion were conducted on the test chip mounted substrates at the same frequency range. Then impedance values in flip-chip interconnection were extracted from cascade transmission matrix. The extracted model parameters of the 100 μm×100 μm interconnect pad show the resistance increases due to skin effect up to 8 GHz. Above this frequency, conductive loss of epoxy resin also increases. Reactance is dominantly affected by inductance of Ni/Au bumps and also conductive particles in the ACF interconnection over the measured frequency range. The inductance value of ACF flip chip interconnection is below 0.05 nH and the contact resistance is below 0.9 R. In addition, the effects of different ACF conductive particle materials on high frequency electrical behavior in GHz range were also investigated, Different ACF conductive particle materials show difference in the reactance, resistance, and resonance frequency behavior up to 13 GHz. Our results indicate that high frequency electrical performance of ACF combined with electroless Ni/Au bump interconnection is acceptable for use in the high frequency flip chip application up to 13 GHz. Finally, 80-ps rise time digital signal transmission with small dispersion low loss reflection was demonstrated through the flip-chip interconnection with combination of ACF and Ni/Au bump View full abstract»

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  • Significant increase of the dielectric performance of plastic sealed telecom relays

    Publication Year: 1999 , Page(s): 567 - 574
    Cited by:  Papers (2)
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    Initialized by Bellcore, the dielectric requirements on telecom relays have been significantly increased in recent years. In parallel the dimensions of the relays had to become smaller and smaller in order to save space on printed circuit boards in electronic equipment. By filling plastic sealed relays with the electro-negative gas sulfur-hexafluoride (SF6), the dielectric withstand voltage of the relays was increased by a factor of 2 compared to that with a normal gasfilling with nitrogen. This method allows one to guarantee a lightning impulse withstand voltage of more than 3500 V between coil and contacts and more than 2500 V between open contacts without increasing distances in the design of the relay. The consequences of a SF6 -filling on the life endurance of a relay were investigated extensively. The results show that the switching range of SF6 filled relays could even be extended compared to relays with a N2 -filling. The gas tightness of the relay housing is sufficient to guarantee an SF6 loss of less than 10% during a lifetime of more than 25 years even under severe climatic conditions. The effects on the environment of using SF6 in telecom relays turn out to be not significant at all View full abstract»

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  • Resolution of broadband transducers in acoustic microscopy of encapsulated ICs: transducer selection

    Publication Year: 1999 , Page(s): 582 - 592
    Cited by:  Papers (15)
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    The lateral resolution of broadband transducers commonly used in acoustic microscopy is discussed in the context of selecting optimum transducers to make images for the best possible resolution of defects in plastic encapsulated integrated circuit (IC) packages. A predictive model to accurately calculate the effective lateral resolution afforded by a transducer is proposed. The model, which explicitly considers the measured frequency dependent attenuation behavior in water and in encapsulant materials, is a practical tool for the acoustic microscopist interested in selecting a transducer with optimum characteristics for inspecting a particular IC package. Experimental data from plastic quad flat packages (PQFP's) molded with two different encapsulants-Nitto MP8000CH and Sumitomo 6300HJ are presented to demonstrate the validity of the modeling approach. Recommendations for optimum transducer selection are presented based on a parametric study of the effect of various transducer and material parameters on the effective lateral resolution and signal loss View full abstract»

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  • Adhesion issues in flip-chip on organic modules

    Publication Year: 1999 , Page(s): 519 - 524
    Cited by:  Papers (8)
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    Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses View full abstract»

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  • An integrated modeling approach to solder joint formation

    Publication Year: 1999 , Page(s): 497 - 502
    Cited by:  Papers (7)
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    The attachment of electronic components to printed circuit boards using solder material is a complex process. This paper presents a novel modeling methodology, which integrates the governing physics taking place. Multiphysics modeling technology, imbedded into the simulation tool-PHYSICA is used to simulate fluid flow, heat transfer, solidification and stress evolution in an integrated manner. Results using this code are presented, detailing the mechanical response of two solder materials as they cool, solidify and then deform. The shape that a solder joint takes upon melting is predicted using the SURFACE EVOLVER code. Details are given on how these predictions can be used in the PHYSICA code to provide a modeling route by which the shape, solidification history, and resulting stress profiles can be predicted View full abstract»

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  • Properties of molding compounds to improve package reliability of SMDs

    Publication Year: 1999 , Page(s): 534 - 540
    Cited by:  Papers (3)
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    Package cracking during reflow soldering process is the great problem in the reliability of plastic packages. The technique of lowering the glass transition temperature (Tg) of a molding compound is very effective for improvement of the package cracking resistance because of the properties of low moisture absorption and high adhesion strength for a molding compound. But the package reliability except for the package cracking resistance is also important. In this study, the effects of the Tg for molding compounds on the package reliability was discussed. It was confirmed that decreasing the crosslinking density was an important factor to improve the package cracking resistance. There was no problem in thermal resistance, even if the molding compound has low Tg. However, decreasing the crosslinking density by the lowering of Tg may not satisfy humidity resistance in some cases. It was found to be important to decrease the crosslinking density of molding compounds without lowering Tg in order to improve both the package cracking resistance and the humidity resistance. It was also confirmed that the introduction of rigid structural segments into the matrix resin molecules of the molding compound was a useful technique for achieving excellent package reliability View full abstract»

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  • Address to the fifth national symposium on reliability and quality control

    Publication Year: 1999 , Page(s): 594 - 596
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    First Page of the Article
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  • Void-effect modeling of flip-chip encapsulation on ceramic substrate

    Publication Year: 1999 , Page(s): 484 - 487
    Cited by:  Papers (3)
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    A detailed numerical and experimental study of the thermal-mechanical stress and strain in the solder bumps (C4s) of a flip-chip ceramic chip carrier has been completed. The numerical model used was based upon the finite element method. The model simulated accelerated thermal cycling (ATC) from 0°C to 100°C. Several parametric studies were conducted, including the effects of chip size, micro-encapsulation, and the effect of the presence of voids in the micro-encapsulant. It was notably found that the presence of voids in the encapsulant does not significantly increase the stress/strain in the C4s, with the exception of very large voids and voids at or near the edge of the chip View full abstract»

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  • Finite element analysis of interface cracking in semiconductor packages

    Publication Year: 1999 , Page(s): 503 - 511
    Cited by:  Papers (4)
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    The application of enriched crack tip finite elements for the prediction of interface fracture parameters, e.g., strain energy release rate and mixed mode stress intensity factors, is presented. Of particular interest, is the comparison between fracture results obtained from two-dimensional (2-D) models and related three-dimensional (3-D) (generalized plane strain) calculations. These results show that for thermal cycling problems, one cannot anticipate 3-D fracture results based on 2-D calculations alone, i.e., plane stress, plane strain, and axisymmetric models. On the other hand, it is shown that the 2-D models are quite adequate for modeling interface fracture in the case of pressure loading on the interface, e.g., pressure due to water vapor expansion during solder reflow. The fracture results presented in this paper were obtained using special enriched crack tip elements that contain the analytic asymptotic displacement and stress field. Enriched crack tip elements for 2-D and 3-D elements are shown to provide highly accurate results for simulating debonding in semiconductor packages subjected to thermal cycling and/or moisture absorption View full abstract»

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  • Effect of BOE etching time on wire bonding quality

    Publication Year: 1999 , Page(s): 551 - 557
    Cited by:  Papers (3)
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    The dependence of wire bond-pull strength on the morphology of the underlying polycrystalline silicon (poly-Si) beneath the bondpad metal is studied using atomic force microscopy (AFM). Statistical analysis shows that the roughness of the poly-Si is correlated with the wire bond-pull strength. The correlation is believed to be due to the effectiveness of thermal dissipation through poly-Si during the wire bonding process. Statistical analysis also shows that the roughness of the poly-Si is correlated to the buffered oxide etch (BOE) etching time before the bondpad metal deposition. In this work, it is concluded that the BOE etching time has a significant effect on the wire bonding quality. The roughness parameter that links the BOE etching time to the wire bond-pull strength is found to be the localization factor View full abstract»

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  • Solder joint reliability of high I/O ceramic-ball-grid arrays and ceramic quad-flat-packs in computer environments: the PowerPC 603TM and PowerPC 604TM microprocessors

    Publication Year: 1999 , Page(s): 488 - 496
    Cited by:  Papers (6)
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    Recent trends in wafer fabrication techniques have produced devices with smaller feature dimensions, increasing gate count and chip inputs/outputs (I/Os). This trend has placed increased emphasis on microelectronics packaging. Surface-mountable packages such as the ceramic quad-flat-pack (CQFP) have provided solutions for many high I/O package issues. As the I/O count gets higher, the pitch has been driven smaller to the point where other solutions also become attractive. Surface-mountable ceramic-ball-grid array (CBGA) packages have proven to be good solutions in a variety of applications as designers seek to maximize electrical performance, reduce printed-circuit board real estate, and improve manufacturing process yields. In support of the PowerPC 603 and PowerPC 604 microprocessors, 21 mm CBGA (255 I/Os) and 32 mm (240 I/Os) and 40 mm (304 I/Os) CQFPs are being utilized. Both package types successfully meet computer environment applications. This paper describes test board assembly processes, accelerated thermal stress test setup, and solder joint failure criteria. Failure mechanisms for both packaging technologies will also be presented. The packages discussed in this paper were subjected to two accelerated thermal cycling conditions: 0 to 100°C and -40 to 125°C. The failure data are plotted using Weibull distributions. The accelerated failure distributions were used to predict failure distributions in application space for typical PowerPC 603 and PowerPC 604 microprocessors computer environments. To predict solder joint reliability of surface-mount technology, a key parameter is: the temperature rise above ambient at the solder joint, ΔT. In-situ field temperature measurements were taken for a range of computer platforms in an office environment, at the central-processing units. Printed-circuit boards (PCB) were not uniform, therefore only maximum temperature regions of the board were measured. These maximum temperatures revealed the mean to be less than 20°C above ambient (i.e., ΔT<20°C) regardless of the power of the device. The largest ΔT measured in any system was less than 30°C above ambient. These temperature measurements of actual computer systems are in close agreement with IPC-SM-785. By utilizing the measured PCB temperature rise, solder joint fatigue life was calculated for the 21 mm ceramic ball-aid-array (CBGA), the package for the PowerPC 603TM and PowerPC 604TM RISC microprocessors. The average on-off ΔT for most computer applications is approximately 20°C. For an average on-off ΔT of 30°C, the 21 mm CBGA has an estimated fatigue life of over 25 years while the 32 mm and 40 mm CQFP's have an estimated fatigue life of over 50 years View full abstract»

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  • Influence of temperature, humidity, and defect location on delamination in plastic IC packages

    Publication Year: 1999 , Page(s): 512 - 518
    Cited by:  Papers (31)
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    The modified J-integral and the stress intensity factor based on linear elastic fracture mechanics can be applied to predict the growth of interfacial delamination in integrated circuit (IC) packages. One of the key parameters required is the interfacial fracture toughness. This paper describes the measurement of the interfacial fracture toughness as a function of temperature and relative humidity using a three-point bending test. The interfacial fracture toughness was found to decrease with temperature and relative humidity. It is proposed that delaminations propagate from very small voids or defects present at the interface. The effect of the location of these interfacial defects or cracks on delamination was studied. The IC package evaluated in this paper was an 80-pin quad flat package with a 0.2 mm defect or crack at the edge or at the center of the interface. It was found that as the temperature of the package was increased, the stress intensity factor of the edge crack was higher than that of the center crack. However, whether the edge crack will propagate first as temperature is increased depends on the ratio of mode II interface toughness to that of the mode I interface toughness. For the package under investigation, it was established that when this ratio is less than 2.69 the edge crack would propagate first, otherwise the center crack would. For small defects, it was found that the water vapor pressure developed at the interface did not have a significant effect on the value of the crack-tip stress intensity factor View full abstract»

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  • Numerical analysis of fine lead bonding-effect of pad mechanical properties on interfacial deformation

    Publication Year: 1999 , Page(s): 558 - 566
    Cited by:  Papers (2)
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    The present study was carried out for the purpose of understanding solid state inner and middle lead bonding, especially the effect of pad mechanical properties on the interfacial deformation processes between lead and pad based on a computer simulation that was carried out by using a finite element method (FEM). As the mechanical properties largely depend on temperature, we discuss the influence of temperature on the effect of pad mechanical properties, i.e., the pad temperature is different from the lead temperature. It is suggested that the interfacial extension reaches greater than 20% for only 10% lead reduction as the pad temperature is 200 K higher than the lead temperature. We further discuss the effect of the substrate temperature on the bond strength, based on the calculated and experimental results View full abstract»

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  • The accuracy of structural approximations employed in analysis of area array packages

    Publication Year: 1999 , Page(s): 525 - 533
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    At the present time, area-array packages are a very common electronics packaging approach. One of the major concerns in designing such packages is the reliability of solder joints, die, and the various material interfaces present in the package. Currently, analytical, numerical, and experimental methods are employed in the analysis of thermo-mechanical stresses/strains in area array packages. The sources of error in these analytical and numerical models may be broadly characterized as being due to geometry representation, material behavior, solution procedure, and due to the accuracy in representing the load history. In this paper we assess the errors in package models due to geometry representation and material behavior using a representative area-array package, namely the 225 input/output (I/O) plastic ball grid array (PBGA). The package deformation due to a fixed temperature change is experimentally characterized using Moire interferometry and numerically simulated using both two- and three-dimensional finite element models. The difference in behavior between the finite element prediction and experimental results is explained using solder material behavior data available in the literature. A comparison of accuracy as well as efficiency is made between the different finite element models. Finally, conclusions are drawn on the aspects of package construction and material that influence behavior, and on the most efficient finite element model to accurately capture this behavior View full abstract»

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Aims & Scope

IEEE Transactions on Components and Packaging Technologies publishes research and applications articles on the modeling, building blocks, technical infrastructure, and analysis underpinning electronic, photonic, MEMS and sensor packaging.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

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Meet Our Editors

Editor-in-Chief
Koneru Ramakrishna
Freescale Semiconductor, Inc.