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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 12 • Date Dec. 1999

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Displaying Results 1 - 14 of 14
  • Crosstalk in VLSI interconnections

    Page(s): 1817 - 1824
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    We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input excitation. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk. View full abstract»

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  • Author index

    Page(s): 1 - 6
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    Freely Available from IEEE
  • Subject index

    Page(s): 6 - 20
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    Freely Available from IEEE
  • Voltage- and current-based fault simulation for interconnect open defects

    Page(s): 1768 - 1779
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    This paper describes a highly accurate and efficient fault simulator for interconnect opens in combinational or full-scan digital CMOS circuits. The analog behavior of the wires with interconnect opens is modeled very efficiently in the vicinity of the defect in order to predict what logic levels the fanout gates will interpret and whether a sufficient IDDQ current will be flowing inside the fanout gates. The fault simulation method is based on characterizing the standard cell library with SPICE, using transistor charge equations for the site of the open, using logic simulation for the rest of the circuit, taking four different factors that can affect the voltage of an open into account, and considering the potential oscillation and sequential behavior of interconnect opens. The tool can simulate test vectors for both voltage and current measurements. Simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets are presented View full abstract»

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  • Wire-sizing optimization with inductance consideration using transmission-line model

    Page(s): 1759 - 1767
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    Because of the inaccuracy of the Elmore delay model and its inability to handle inductance, it is necessary to use a more accurate delay model in wire-sizing optimization. This paper presents continuous wire-sizing optimization by using a three pole based delay model. Our work is focused on exponential wire shape f(x)=ae-bx, i.e, we determine a and b such that either delay or area is minimized. Fringing capacitance and inductance, which have been neglected in previous work on wire sizing, are taken into consideration in the delay model. Expressions involved in calculating all three poles are derived with the help of the Picard-Carson method. Since these expressions are all analytical, the delay calculation is very efficient. In our experiments, the delay model is found to be far more accurate than the Elmore delay model. We also observe that in determining the optimal shape that minimizes delay, the Elmore delay model performs as well as our delay model. However, in determining the optimal shape that minimizes area subject to a delay bound, the Elmore delay model performs much worse than our delay model View full abstract»

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  • A synthesis for testability scheme for finite state machines using clock control

    Page(s): 1780 - 1792
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    A new method is proposed for improving the testability of a finite state machine (FSM) during its synthesis. The method exploits clock control to enhance the controllability and observability of machine states. With clock control it is possible to add new state transitions during testing. Therefore, it is easier to navigate between states in the resulting test machine. Unlike prior work, where clock control is added to the circuit as a post-design step, here, clock control is considered in conjunction with a symbolic scheme for encoding the states of the FSM. The encoding is shown to result in significant reductions in the interstate distances in the benchmark FSM's. Further, the observability of the encoded states can be improved by adding two primary outputs to the circuit such that a fixed input sequence forms a distinguishing sequence for all states. Theoretical results show that for a large class of FSM's, the testability improvements are comparable to those achievable by scan designs. Experimental results show that available test pattern generation tools are able to take advantage of the enhanced testability in producing shorter test sequences, particularly for machines with poor connectivity of states View full abstract»

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  • High-level synthesis of low-power control-flow intensive circuits

    Page(s): 1715 - 1729
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    In this paper, we present a comprehensive high-level synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. An iterative improvement framework allows the system to search the design space by examining the interaction between the different high-level synthesis tasks. In addition to incorporating traditional high-level synthesis tasks such as scheduling, module selection and resource sharing, we introduce a new optimization that performs power-conscious structuring of multiplexer networks, which are predominant in control-flow intensive circuits. The scheduler employed is capable of loop optimizations within and across loop boundaries. We also introduce a fast power estimation technique, based on switching activity matrices, to drive the synthesis process. Experimental results for a number of control-flow intensive and data-dominated benchmarks demonstrate power reduction of up to 62% (58%) when compared to Vdd-scaled area-optimized (delay-optimized) designs. The area overheads over area-optimized designs are less than 39%, whereas the area savings over delay-optimized designs are up to 40% View full abstract»

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  • Design error diagnosis and correction via test vector simulation

    Page(s): 1803 - 1816
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    With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits View full abstract»

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  • Linear gate assignment: a fast statistical mechanics approach

    Page(s): 1750 - 1758
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    This paper deals with the problem of linear gate assignment in two layout styles: one-dimensional logic array and gate matrix layout. The goal is to find the optimal sequencing of gates in order to minimize the required number of tracks, and thus to reduce the overall circuit layout area. This is known to be an NP-hard optimization problem, for which no absolute approximation algorithm exists. Here we report the use of a new optimization heuristic derived from statistical mechanics-the microcanonical optimization algorithm, μ0-to solve the linear gate assignment problem. Our numerical results show that μ0 compares favorably with at least five previously employed heuristics: simulated annealing, the unidirectional and the bidirectional Hong construction methods, and the artificial intelligence heuristics GM Plan and GM Learn. We also show how the algorithm is able to outperform microcanonical annealing. Moreover, in a massive set of experiments with circuits whose optimal layout is not known, our algorithm has been able to match and even to improve, by as much as seven tracks, the best solutions known so far View full abstract»

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  • Three-dimensional simulation of HPCVD-linking continuum transport and reaction kinetics with topography simulation

    Page(s): 1741 - 1749
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    For wafer sizes in state of-the-art semiconductor manufacturing ranging up to 300 mm, the uniformity of processes across the wafer becomes a very important issue. We present a fully three-dimensional model for the feature scale simulation of continuum transport and reaction determined high-pressure chemical vapor deposition processes suitable for the investigation of such nonuniformities. The newly developed three-dimensional approach combines topography simulation, meshing, and finite element method tools, and allows simulations over arbitrary geometries such as structures resulting from nonuniform underlying physical vapor deposition films. This enables the examination of film profile variations across the wafer for multistep processes consisting of low- and high-pressure parts such as Ti/TiN/W plug-fills, Additionally, the model allows a very flexible formulation of the involved gas chemistry and surface reactions and can easily be extended to process chemistries including gas phase reactions of precursors as observed in deposition of silicon dioxide from tetraethylorthosilicate (TEOS). We show simulation examples for a tungsten deposition process, which is applied as last step in a Ti/TiN/W plug-fill. For filling of an L-shaped trench, we show the transition from transport to reaction limited process conditions View full abstract»

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  • Broadcasting test patterns to multiple circuits

    Page(s): 1793 - 1802
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    Scan designs can alleviate test difficulties of sequential circuits by replacing the memory elements with scannable registers. However, scan operations usually result in long test application time. Most classical methods to solving this problem either perform test compaction to obtain fewer test vectors or use multiple scan chain design to reduce the scan time. For a large system, test vector compaction is a time-consuming process, while multiple scan chains either require extra pin overhead or need the sharing of normal I/O and scan I/O pins. In this paper, we present a novel test methodology that not only substantially reduces the total test pattern number for multiple circuits but also allows a single input data line to support multiple scan chains. Our main idea is to explore the “sharing” property of test patterns among all circuits under test (CUT's). By appropriately connecting the inputs of all CUT's during the automatic test-pattern generation process such that the generated test patterns can be broadcast to all scan chains when the actual testing operation is executed, the above-mentioned problems can be solved effectively. Our method also provides a low-cost and high-performance method to integrate the boundary scan and scan architectures. Experimental results show that 157 test patterns are enough to detect all detectable faults in the ten ISCAS'85 combinational circuits, while 280 are enough for the ten largest ISCAS'89 scan-based sequential circuits View full abstract»

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  • A physics-based semiconductor noise model suitable for efficient numerical implementation

    Page(s): 1730 - 1740
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    A semiconductor device noise model in the framework of semiclassical transport and Pauli's exclusion principle is presented. Terminal current noise is modeled as a direct consequence of electron scattering taking place inside the device at the microscopic level. The approach directly connects electron scattering rates of semiclassical transport theory with the current spectral density at the device terminals. It is shown that the spectral density of steady-state current fluctuations can be obtained from the transient solution of the Boltzmann transport equation with special initial conditions. This formulation is inherently suitable for deterministic solution techniques, for instance, the computationally efficient spherical harmonics method. Approximating the instantaneous value of the occupation number by the occupation probability, this model is able to account for Pauli's principle and at the same time describe the behavior of the electron ensemble in terms of independent entities. As a practical demonstration, the model is employed to compute the current noise spectral density due to generation recombination and acoustic and optical phonon scattering for bulk n-type silicon material. Additionally, in order to add more physical insight and to verify results, the model is also employed to compute the low-frequency current spectral density as a function of the electric field and temperature, respectively. The results show good agreement with low-frequency noise measurements reported in literature View full abstract»

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  • Power optimization of variable-voltage core-based systems

    Page(s): 1702 - 1714
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    The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We developed the design methodology for the low-power core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrial strength multimedia and communication applications View full abstract»

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  • SAMC: a code compression algorithm for embedded processors

    Page(s): 1689 - 1701
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    In this paper, we present a method for reducing the memory requirements of an embedded system by using code compression. We compress the instruction segment of the executable running on the embedded system, and we show how to design a run-time decompression unit to decompress code on the fly before execution. Our algorithm uses arithmetic coding in combination with a Markov model, which is adapted to the instruction set and the application. We provide experimental results on two architectures, Analog Devices' Share and ARM's ARM and Thumb instruction sets, and show that programs can often be reduced by more than 50%. Furthermore, we suggest a table-based design that allows multibit decoding to speed up decompression View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu