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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 1999

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Displaying Results 1 - 18 of 18
  • Comments on "Negative capacitance effect in semiconductor devices" [by M. Ershov et al., with reply]

    Publication Year: 1999 , Page(s): 2357 - 2358
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (41 KB)  

    For original paper, see M. Ershov et al., ibid., vol. 45, pp. 2196-2206 (Oct. 1998). The original authors tried to interpret the negative capacitance (NC) phenomenon theoretically in physics. However, the commentators point out that the definition of capacitor from I=(G+jB) V used in the paper is not correct. Using an R-L-C resonance circuit they interpret the so-called NC, that is just an inductive effect. Instead of using the conventional R-C equivalent circuit model for a diode, one should use an R-C-L resonance circuit as the equivalent circuit for the diode. In reply, Ershov et al. assert that they proposed a convenient and physically sound approach to NC treatment based on transient current analysis and highlighted typical mistakes involved in NC interpretation. They refute the criticism of the definition of capacitance in terms of admittance made by the commentators. View full abstract»

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  • Author index

    Publication Year: 1999 , Page(s): 1 - 16
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    Freely Available from IEEE
  • Subject index

    Publication Year: 1999 , Page(s): 16 - 49
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    Freely Available from IEEE
  • Characteristics of InAlAs/InGaAs high-electron-mobility transistors under illumination with modulated light

    Publication Year: 1999 , Page(s): 2271 - 2277
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    The optical response of InAlAs/InGaAs HEMT's under illumination with modulated light from a 1.3-μm semiconductor laser diode onto the backside of the substrate is measured by using an optical-signal analyzer. It is clear that the response is composed of two signals. One signal is dominant at a low frequency and is due to the photovoltaic effect that causes excess holes photogenerated in the InGaAs channel to accumulate in the source region. This accumulation thus causes a decrease in the threshold voltage of the HEMTs. To explain this mechanism, a theory is given which connects the change in threshold voltage with that in the Fermi energy of the two-dimensional electron gas (2-DEG). The other signal is dominant at a high-frequency and is due to the photoconductive effect in the InGaAs channel beneath the gate. In this case, a large optical gain is produced since electrons at the source region are replenished in the gate channel. This leads to the first clear observation of a photoconductive signal. The bandwidth due to the photovoltaic effect is as low as 45 MHz and is dominated by the lifetime of the excess holes. The bandwidth due to the photoconductive effect is as high as 37 GHz and is dominated by the gain-bandwidth product of transistors rather than the intrinsic transit-time of electrons View full abstract»

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  • Effects of thermal processes after silicidation on the performance of TiSi2/polysilicon gate device

    Publication Year: 1999 , Page(s): 2353 - 2356
    Cited by:  Papers (3)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    The effects of thermal processes after silicidation on the gate depletion, threshold voltage (Vth) shift, drive current, and sheet resistance of TiSi2/polysilicon (Ti-polycide) gate devices are evaluated. The dopant depletion of the polysilicon film, which is known to increase the Vth and to degrade the drive-current, increases with increasing temperature of the post-thermal process. However, the Vth roll-off characteristic in nMOSFETs is enhanced with increasing temperature. Furthermore, the drive-current is significantly degraded by the gate reoxidation process. The sheet resistance of the Ti-polycide gate increases with gate reoxidation as well as with increased post-thermal processes View full abstract»

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  • A solar blind, hybrid III-nitride/silicon, ultraviolet avalanche photodiode

    Publication Year: 1999 , Page(s): 2348 - 2350
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB)  

    A novel, hybrid III-Nitride/Si, ultraviolet (UV) avalanche photodiode (APD) is proposed. The device combines the favorable short wavelength interband absorption properties of the direct bandgap III-Nitride material with the unique impact ionization characteristics of silicon. Solar blind response is achieved through optical isolation of the multiplication region of the device View full abstract»

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  • Enhanced injection in n++-poly/SiOx/SiO2 /p-sub MOS capacitors for low-voltage nonvolatile memory applications: experiment

    Publication Year: 1999 , Page(s): 2315 - 2322
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    In this paper, n++-poly/SiOx/SiO2/p-sub capacitors with enhanced electron injection under substrate accumulation are extensively studied. First, systematic investigation of the role of technology parameters in the PECVD deposition of the SiOx films is presented. In particular, the effect of the silane dilution parameter on the device performance is investigated and the SiOx film optimized in terms of reliability and electron injection enhancement. Then, investigation of the electrical behavior of n++ -poly/SiOx/SiO2/p-sub MOS capacitors is presented. As a result, a picture of the space defect distribution in the SiOx films is proposed. In SiOx films, a relevant density of trapped charge adds to ionized impurities. In particular, the net charge is negative in the bulk of the dielectric, indicating that trapped electrons exceed all the other charge contributions. The space distribution of defects is strongly nonuniform and has the maximum in the vicinity of the SiOx/SiO2 interface. After dc current stress, the devices undergo electrical degradation, the dominant mechanism of degradation being the creation of interface hole traps. The trap generation model is based on the release of hydrogen and pairs generation in the SiOx films. The time-scale of trap filling during the stress is tens of seconds, which suggests that the stress-induced traps are deep in the energy gap View full abstract»

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  • A physically-based C-continuous model for accumulation-mode SOI pMOSFETs

    Publication Year: 1999 , Page(s): 2295 - 2303
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    In this paper, we present a unified accumulation-mode (AM) SOI MOSFET model for circuit simulation. The model is valid in all the regimes of normal operation and includes explicit expressions of the drain current and total charges which have an infinite order of continuity; therefore, smooth transitions are assured. Short-channel effects have also been accounted for. We have finally proved that our model accurately fits the transistor characteristics for effective channel lengths down to 0.7-μm View full abstract»

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  • Dynamic snap-back induced programming failure in stacked gate flash EEPROM cells and efficient remedying technique

    Publication Year: 1999 , Page(s): 2340 - 2343
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    A new kind of programming failure is reported in stacked gate Flash EEPROM cells and its remedying scheme is presented. The failure is observed under typical bit line (B/L) disturbance bias conditions but is different from the case of the drain turn-on induced leakage current over-burdening the charge pumping. Rather, its root cause is identified for the first time to be the dynamic snap back breakdown operative in the memory cell. This snap-back induced programming failure is shown effectively mitigated with the use of an appropriate series resistance in the source loop of the memory cell. The remedying role of the source series resistance is discussed View full abstract»

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  • Interface properties of NO-annealed N2O-grown oxynitride

    Publication Year: 1999 , Page(s): 2311 - 2314
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB)  

    The oxide/Si interface properties of gate dielectric prepared by annealing N2O-grown oxide in an NO ambient are intensively investigated and compared to those of O2-grown oxide with the same annealing conditions. Hot-carrier stressings show that the former has a harder oxide/Si interface and near-interface oxide than the latter. As confirmed by SIMS analysis, this is associated with a higher nitrogen peak concentration near the oxide/Si interface and a larger total nitrogen content in the former, both arising from the initial oxidation in N2O instead of O2 View full abstract»

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  • Analysis of GaAs OPFET with improved optical absorption under back illumination

    Publication Year: 1999 , Page(s): 2350 - 2353
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    The effect of back illumination with improved optical absorption has been analyzed for an ion-implanted GaAs OPFET considering the Pearson IV distribution of impurities. Plots have been made for two photo voltages developed across the substrate active layer junction and the Schottky junction. The drain-source current is significantly enhanced for the device when a fiber is inserted up to the active layer substrate junction compared with the case where the finite substrate effect is taken into account View full abstract»

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  • Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display

    Publication Year: 1999 , Page(s): 2282 - 2288
    Cited by:  Papers (84)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A high-resolution low-temperature polysilicon thin-film transistor driven light emitting polymer display (LT p-Si TFT LEPD) with integrated drivers has been developed. We adopted conductance control of the TFT and optimized design and voltage in order to achieve good gray scale and simple pixel circuit. A p-channel TFT is used in order to guarantee reliability in dc bias. An inter-layer reduces parasitic capacitance of bus lines. Because of the combination of the LT p-Si TFT and LEP, the display is thin, compact, and lightweight, as well as having low power consumption, wide viewing angle, and fast response View full abstract»

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  • Temperature and optical characteristics of tin oxide membrane gate ISFET

    Publication Year: 1999 , Page(s): 2278 - 2281
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    The influence of temperature and optical effects on ISFET performance are important. In this study, the temperature characteristics of the SnO2/Si3N4/SiO 2/Si ISFET are investigated by the zero temperature coefficient (T.C.) adjustment and the dual FET's configuration, respectively. The result show that a zero T.C. of the SnO2 gate ISFET can be achieved when the appropriate operation current was set. Subsequently, the T.C. of tin oxide membrane/electrolyte interface can be evaluated by the dual FETs configuration. On the other hand, due to the SnO2 gate ISFET is sensitive to the light exposure, thus in order to improve this drawback, a multi-structure ISFETs: SnO 2/Al/SiO2/Si3N4/Si ISFETs have been developed. In this structure, aluminum is used as a light shield, and the tin oxide is used as a pH sensitive layer. The results show the ISFETs with aluminum as a light shield have low light sensitivity compared with ISFETs without aluminum as a light shield View full abstract»

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  • Characterization and profile optimization of SiGe pFETs on silicon-on-sapphire

    Publication Year: 1999 , Page(s): 2323 - 2332
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    We present the details of the fabrication, electrical characterization, and profile optimization of a SiGe pFET on silicon-on-sapphire (SOS) technology. The results show that the SiGe pFETs have higher low-field mobility (μeff), transconductance (gm), and cutoff frequency (fT) than a comparable Si pFET. At low temperature (85 K), a secondary peak is observed in the linear gm of the SiGe pFETs and is attributed to hole confinement in the SiGe channel. The effect of reducing the SOS film thickness on the mobility and short-channel performance is studied. A low-frequency noise study shows significant improvement in the SiGe pPETs over comparable Si pFETs, and is attributed to a lower sampling of interface trap density caused by the band offset at the oxide interface due to SiGe. Drain Induced Back Channel Inversion (DIBCI) is shown to occur in short gate length devices, resulting in high off-state leakage current through conduction at the back silicon-sapphire interface. The paper also discusses important optimization issues in the design of 0.25-μm gate length SiGe pFETs. A novel structure is proposed which optimizes the threshold voltage, maximizes hole confinement gate voltage range and cutoff frequency, while at the same time minimizing DIBCI to make the design usable to gate lengths as short as 0.25 μm View full abstract»

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  • The characteristics of plasma display with the cylindrical hollow cathode

    Publication Year: 1999 , Page(s): 2344 - 2347
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    A newly designed plasma display with a cylindrical hollow cathode has been proposed and investigated to study the relationship between the photoluminous efficiency and the discharge characteristics. The photoluminous efficiency and discharge characteristics are dependent on the geometry factors of the cylindrical hollow cathode and gas pressure in the plasma display. When p×d (where p is the gas pressure and d is the hole diameter of the cylindrical hollow cathode) is below 2 torr·cm, the plasma display has as much as five times higher luminous efficiency compared to that for p×d above 2 torr·cm and it also shows a positive current-voltage (I-V) slope as in an abnormal glow View full abstract»

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  • Effects of Ir electrodes on barium strontium titanate thin-film capacitors for high-density memory application

    Publication Year: 1999 , Page(s): 2304 - 2310
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    Excellent electrical characteristics of RF-sputtered Barium Strontium Titanate (BST) thin-film capacitors with iridium (Ir) electrodes were obtained and the influence of Ir on device properties was investigated. In contrast to conventional Pt-electroded system, BST capacitors with Ir electrodes exhibit higher polarization and slightly higher leakage current. The stronger crystallinity of a thin BST layer (~70 Å) initially grown on Ir substrate is believed to be the cause for higher charge storage density of the Ir-electroded capacitors. However, this higher polarization is accompanied by higher dielectric dispersion (3.12% per decade for Ir versus 1.98% for Pt electrodes). On the other hand, leakage current appears to be dominated by the Schottky barrier formed by Ir-BST and Pt-BST contacts, respectively, at high field. The analysis from temperature-dependent J-V data indicates a lower barrier height for the Ir-BST contact than Pt-BST contact. The slightly higher leakage current density of the BST capacitors with Ir electrodes can thus be attributed to the lower barrier height View full abstract»

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  • A physics-based dynamic thermal impedance model for vertical bipolar transistors on SOI substrates

    Publication Year: 1999 , Page(s): 2333 - 2339
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    A physics-based compact model for the thermal impedance of vertical bipolar transistors, fabricated with full dielectric isolation, is presented. The model compares favorably to both three dimensional (3-D) ANSYS(R) transient simulations and measurements. Using the software package Thermal Impedance Pre-Processor (TIPP), a multiple-pole circuit can be fitted to the thermal impedance model. The thermal equivalent circuit is used in conjunction with a modified version of SPICE to give efficient electrothermal simulations in the dc and transient regimes View full abstract»

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  • The dynamic response analysis of a pyroelectric thin-film infrared sensor with thermal isolation improvement structure

    Publication Year: 1999 , Page(s): 2289 - 2294
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    Both theoretical and experimental studies of the substrate effect on the thermal behavior of a PbTiO3 infrared (IR) sensor have been reported. With active cantilever dimensions of 200×100×5 μm3 formed by etching processes, the pyroelectric micro-electro-mechanical system (pyro/MEMS) structure exhibits a much superior performance to that of a traditional IR-sensing bulk structure under the 800-μW incident optical light with wavelength of 970 nm. Two-order improvement in current responsivity is obtained for the pyro/MEMS structure. This shows the substrate effect on the performance of a pyro/MEMS IR sensor is very significant. A simple model has also been proposed to illustrate the substrate effect more comprehensively View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego