IEEE Transactions on Computers

Issue 1 • Jan 1990

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Displaying Results 1 - 20 of 20
  • Addressing, routing, and broadcasting in hexagonal mesh multiprocessors

    Publication Year: 1990, Page(s):10 - 18
    Cited by:  Papers (91)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (808 KB)

    A family of six-regular graphs, called hexagonal meshes or H-meshes, is considered as a multiprocessor interconnection network. Processing nodes on the periphery of an H-mesh are first wrapped around to achieve regularity and homogeneity. The diameter of a wrapped H-mesh is shown to be of O(p1/2 ), where p is the number of nodes in the H<... View full abstract»

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  • Optimal robust compression of test responses

    Publication Year: 1990, Page(s):138 - 141
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (404 KB)

    A compression of test responses technique for a built-in self-test (BIST) VLSI design is presented. The authors introduce the notion of a robust compression technique which incorporates prior knowledge of the statistics of fault-free responses under pseudorandom testing to achieve a guaranteed error detectability independent of a distribution of errors. The presented robust quadratic compressor re... View full abstract»

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  • Further comments, with reply, on `Detection of faults in programmable logic arrays' by J.E. Smith

    Publication Year: 1990, Page(s):155 - 157
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (188 KB)

    In recent correspondence, L. Ye-Wei and J. Wei (see ibid., vol.C-35, p.930-1 (1986)) have shown two counterexamples that contradict theorems four and five of a paper by J.E. Smith (see ibid., vol.C-28, p.845-53 (1979)). In his reply, Smith (see ibid., vol.C-35, p.931 (1986)) stated an additional condition under which the theorems hold good. The commenters provide a counterexample that contradicts ... View full abstract»

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  • A checkpointing page store for write-once optical disk

    Publication Year: 1990, Page(s):2 - 9
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (724 KB)

    A model paging system is described for write-once optical disk. The paging system checkpoints pages on a nonerasable, failure-resistant medium as a side effect of virtual memory operation. Most pages are already checkpointed at any given time. It is practicable to checkpoint the global state periodically by forcing the write-out of pages that have been modified since their last checkpoint, togethe... View full abstract»

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  • Parallel Quicksort using fetch-and-add

    Publication Year: 1990, Page(s):133 - 138
    Cited by:  Papers (12)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (724 KB)

    A parallelization of the Quicksort algorithm that is suitable for execution on a shared memory multiprocessor with an efficient implementation of the fetch-and-add operation is presented. The partitioning phase of Quicksort, which has been considered a serial bottleneck, is cooperatively executed in parallel by many processors through the use of fetch-and-add. The parallel algorithm maintains the ... View full abstract»

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  • A decomposition approach for balancing large-scale acyclic data flow graphs

    Publication Year: 1990, Page(s):34 - 46
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (996 KB)

    An efficient decomposition technique that provides a more systematic approach in solving the optimal buffer assignment problem of an acyclic data-flow graph (ADFG) with a large number of computational nodes is presented. The buffer assignment problem is formulated as an integer linear optimization problem that can be solved in pseudopolynomial time. However, if the size of an ADFG increases, then ... View full abstract»

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  • Recursive moving window DFT algorithm

    Publication Year: 1990, Page(s):145 - 148
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB)

    A recursive algorithm is presented for computing the discrete Fourier transform (DFT). The algorithm is developed for a moving-window-type processing. The computational structure is fully concurrent and allows a vectorized updating of the DFT. The total time required for the updating could be as low as that of only one multiplication and two additions, regardless of the number of points. A possibl... View full abstract»

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  • Computing the singular value decomposition on the Connection Machine

    Publication Year: 1990, Page(s):152 - 155
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (400 KB)

    Consideration is given to the computation of the singular value decomposition (SVD) on the Connection Machine (CM). Brief descriptions of the Lisp language and some typical matrix manipulating functions are given. Implementation details of various Jacobi-SVD algorithms on an 8192-processor CM are presented. For n×n matrices, where n⩽64, the decomposition is com... View full abstract»

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  • Parallel parsing of arithmetic expressions

    Publication Year: 1990, Page(s):130 - 132
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (256 KB)

    Parallel algorithms for parsing expressions on mesh, shuffle, cube, and cube-connected cycle parallel computers are presented. With n processors, it requires O(√n) time on the mesh-connected model and O(log2 n) time on others. For the mesh-connected computer, the author uses a wrap-around row-major ordering. For the shuffle computer, he... View full abstract»

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  • An adaptive algorithm to ensure differential service in a token-ring network

    Publication Year: 1990, Page(s):19 - 33
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (860 KB)

    A distributed and adaptive token-passing algorithm that can be used to maintain the values of a designated performance parameter (e.g. mean waiting time) at the hosts of a token-ring network at a prescribed ratio is presented. The algorithm is simple to implement. The authors demonstrate its application in keeping the mean waiting times at the various hosts in a prespecified ratio, in maintaining ... View full abstract»

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  • A hardware accelerator for maze routing

    Publication Year: 1990, Page(s):141 - 145
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (520 KB)

    A hardware accelerator for the maze routing problem is developed. This accelerator consists of three three-stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency. The design is compared to other proposed designs. Unlike other proposed hardware solutions for this problem, this design does not require an increase in the number of processors as the p... View full abstract»

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  • Performance analysis of a generalized concurrent error detection procedure

    Publication Year: 1990, Page(s):47 - 62
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1124 KB)

    A general procedure for error detection in complex systems, called the data block capture and analysis monitoring process, is described and analyzed. It is assumed that, in addition to being exposed to potential external fault sources, a complex system will in general always contain embedded hardware and software fault mechanisms which can cause the system to perform incorrect computations and/or ... View full abstract»

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  • Stretching a knock-knee layout for multilayer wiring

    Publication Year: 1990, Page(s):148 - 151
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    The problem of stretching a knock-knee layout in the knock-knee mode to ensure its wirability is considered. An optimal algorithm for the problem in two layers is presented. A 4/3 approximation algorithm for the corresponding problem in three layers, shown to be NP-complete, is devised View full abstract»

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  • Design and analysis of a gracefully degrading interleaved memory system

    Publication Year: 1990, Page(s):63 - 71
    Cited by:  Papers (3)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (864 KB)

    The organization of interleaved memories in such a way that faults in the memory system degrade the performance in a graceful manner is studied. Attention is restricted to an interleaved memory system that starts out with 2q memory banks and uses a low-order interleaving scheme. The motivation and design objectives of the memory system are described. A new reconfiguration scheme and the... View full abstract»

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  • Concurrent logic programming as a hardware description tool

    Publication Year: 1990, Page(s):72 - 88
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1576 KB)

    The possibility of developing hardware description languages (HDLs) based on the principles of logic programming is discussed. The specific logic programming language used to demonstrate this possibility is Flat Concurrent Prolog (FCP). It is shown explicitly how FCP naturally satisfies the commonly accepted fundamental requirements of a hardware description language. It is then demonstrated how F... View full abstract»

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  • Generalized signed-digit number systems: a unifying framework for redundant number representations

    Publication Year: 1990, Page(s):89 - 98
    Cited by:  Papers (102)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (808 KB)

    Signed-digit (SD) number representation systems have been defined for any radix r⩾3 with digit values ranging over the set {-α, . . ., -1, 0, 1, . . ., α}, where α is an arbitrary integer in the range 1/2r<α<r. Such number representation systems possess sufficient redundancy to allow for the annihilation of carry or borrow chains and hen... View full abstract»

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  • On the number of acceptable task assignments in distributed computing systems

    Publication Year: 1990, Page(s):99 - 110
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (844 KB)

    A distributed computing system and cooperating tasks can be represented by a processor graph Gp=(Vp, Ep) and a task graph GT=(VT, E T), respectively. An edge between a pair of nodes in GT represents the existence of direct communications between the two corres... View full abstract»

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  • HYTREM-a hybrid text-retrieval machine for large databases

    Publication Year: 1990, Page(s):111 - 123
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1104 KB)

    The design of a text-retrieval machine, called HYTREM (hybrid text-retrieval machine), for the support of large unformatted text databases is described. A signature file is used as an access method to reduce the amount of data that need to be searched directly. Therefore, HYTREM consists of two major subsystems: a signature processor and a text processor. The signature processor is based on a worl... View full abstract»

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  • Crossing minimization in linear embeddings of graphs

    Publication Year: 1990, Page(s):124 - 127
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    The problem of embedding a graph in the plane with the minimum number of edge crossings arises in some circuit layout problems. It has been known to be NP-hard in general. Recently, in the area of book embedding, this problem was shown to be NP-hard even when the vertices are placed on a straight line l. The authors show that the problem remains NP-hard even if, in addition to these const... View full abstract»

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  • A systematic method for division with high average bit skipping

    Publication Year: 1990, Page(s):127 - 130
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    It is shown that, if a division is described by AQ=C , where A is the divisor, Q is the quotient, and C is the dividend, then the bit variables involved in a set of equations, each of which determines a leading bit of C, gives an approximation for Q that an be used in a SRT division scheme. The results of an exhaustive statistical simu... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org