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Computer

Issue 11 • Date Nov. 1999

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Displaying Results 1 - 9 of 9
  • Just curious: An interview with John Cocke

    Publication Year: 1999, Page(s):34 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (695 KB)

    First Page of the Article
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  • Robust scan-based logic test in VDSM technologies

    Publication Year: 1999, Page(s):66 - 74
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (567 KB)

    The customer expects defect-free chips, at consumer prices, making thorough manufacturing test mandatory. With increasing chip density, the addition of say 10,000 gates is no longer of great impact (these would occupy only 0.1 mm2 on a 0.18-μm die); satisfying timing requirements and not exceeding package or system power requirements are the principal implementation objectives. ... View full abstract»

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  • Every little bit counts: toward more reliable software

    Publication Year: 1999, Page(s):131 - 135
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    By and large, software works much of the time, more or less. If society hadn't come to rely so fundamentally on our profession, Y2K, for one, wouldn't be such a big deal. But the overall service that we render is not good enough by any measure. One of the most critical components of software quality is reliability. Efforts to improve reliability are not new. In fact, there are many different appro... View full abstract»

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  • Rethinking deep-submicron circuit design

    Publication Year: 1999, Page(s):25 - 33
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Interconnect delay need not increase as CMOS process geometries shrink, and current IC design methods should suffice for modules of up to 50,000 gates. Beyond that, designers must focus on a new concept - global interconnect design. We consider the effects of both devices and interconnect, and our analysis shows that interconnect delay actually decreases for deep-submicron (DSM) processes in a mod... View full abstract»

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  • Tough challenges as design and test go nanometer

    Publication Year: 1999, Page(s):42 - 45
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    Test engineers are already hard pressed to ensure the quality of ICs despite ever shorter time to market and skyrocketing test costs. Nanometer technologies will only add to the challenge View full abstract»

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  • Nanometer technology effects on fault models for IC testing

    Publication Year: 1999, Page(s):46 - 51
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Accepted methods for testing integrated circuits, such as the fault models examined here, require ongoing research and continual adaptation to accommodate increasing circuit size, growing defect subtlety, and less varied manufacturing processes View full abstract»

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  • Nanometer technology challenges for test and test equipment

    Publication Year: 1999, Page(s):52 - 57
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Designers can now place millions of transistors on a single chip and propagate a signal through them at speeds approaching one gigahertz. With all this progress on the design front, it's easy to overlook a simple fact: more complex designs also pose problems for manufacturing and test. The challenges are especially acute in test. Test costs traditionally rise as frequency, transistors, and pin cou... View full abstract»

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  • Current directions in automatic test-pattern generation

    Publication Year: 1999, Page(s):58 - 64
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Test development automation tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for testability (DFT), test pattern generation, pattern-grading, and test program development and debugging. The focus in the article is on automatic test-pattern-generation tools. Researchers have looked primarily at issues such as scalability, abi... View full abstract»

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  • Today's style sheet standards: the great vision blinded

    Publication Year: 1999, Page(s):123 - 125
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    Our research into style sheet systems and languages (Proteus and PSL) shows that there are alternatives to CSS and XSL that more closely meet the necessary criteria. The PSL style language has a syntax especially designed for the style sheet task and has traditional computational features including mathematical expressions and conditionals. In contrast to XSL, PSL does not emphasize transformation... View full abstract»

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Aims & Scope

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed articles written for and by computer researchers and practitioners representing the full spectrum of computing and information technology, from hardware to software and from emerging research to new applications. 

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Meet Our Editors

Editor-in-Chief
Sumi Helal
University of Florida
sumi.helal@gmail.com