IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • Apr 1990

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Displaying Results 1 - 10 of 10
  • Over-the-cell channel routing

    Publication Year: 1990, Page(s):408 - 418
    Cited by:  Papers (59)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (900 KB)

    A common approach to the over-the-cell channel routing problem is to divide the problem into three steps: (1) routing over the cells; (2) choosing net segments; and (3) routing within the channel. It is shown that the first step can be reduced to the problem and finding a maximum independent set of a circle graph, and thus can be solved optimally in quadratic time. Also, it is shown that to determ... View full abstract»

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  • An optimal Steiner tree algorithm for a net whose terminals lie on the perimeter of a rectangle

    Publication Year: 1990, Page(s):398 - 407
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (880 KB)

    Given a set of input points, the rectilinear Steiner tree problem is to find a minimal-length tree consisting of vertical and horizontal line segments that connects the input points, where it is possible to add new points to minimize the length of the tree. The restricted Steiner tree problem in which all the input points lie on the boundary of a rectangle frequently occurs in VLSI physical design... View full abstract»

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  • Compaction on the torus [VLSI layout]

    Publication Year: 1990, Page(s):389 - 397
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (804 KB)

    A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area. An effective compaction system frees the designer from the details of the design rules, and hence, increases his or her productivity and on the other hand produces high quality layouts. A general framework for compaction on a torus is introduced. This problem comes up whenever an array of identica... View full abstract»

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  • Covering rectilinear polygons by rectangles

    Publication Year: 1990, Page(s):377 - 388
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (952 KB)

    Three approximation algorithms to cover a rectilinear polygon that is neither horizontally nor vertically convex by rectangles are developed. All three guarantee covers that have at most twice as many rectangles as in an optimal cover. One takes O(n log n) time, where n is the number of vertices in the rectilinear polygon. The other two take O(n View full abstract»

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  • Generic linear RC delay modeling for digital CMOS circuits

    Publication Year: 1990, Page(s):367 - 376
    Cited by:  Papers (27)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (816 KB)

    The linear RC delay modeling technique is used to model the timing delays in CMOS circuit empirically. The empirical model, a multidimensional function of various circuit and device parameters, is shown to be simplified to a two-dimensional model which estimates the delay of a CMOS subcircuit in terms of the generic RC delay ad the rise/fall time of the input transition. Accuracy... View full abstract»

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  • Asymptotic waveform evaluation for timing analysis

    Publication Year: 1990, Page(s):352 - 366
    Cited by:  Papers (1164)  |  Patents (47)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1080 KB)

    Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations. The RLC interconnect model may contain floating capacitors, grounded resistors, inductors, and even linear controlled sources. The transient portion of the response is approximated by matching the initial boundary conditions and the first 2q-1 moments of th... View full abstract»

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  • Multilevel verification of MOS circuits

    Publication Year: 1990, Page(s):341 - 351
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1004 KB)

    The ideas behind Silica Pithecus, a program for verifying synchronous digital MOS VLSI circuits, are described. Silica Pithecus accepts the schematic of an MOS VLSI circuit, declarations of the logical relationships between the input signals, and a specification of the intended digital behavior of the circuit. If the circuit fails to meet its specification, Silica Pithecus returns to the designer ... View full abstract»

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  • Probabilistic simulation for reliability analysis of CMOS VLSI circuits

    Publication Year: 1990, Page(s):439 - 450
    Cited by:  Papers (114)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1088 KB)

    A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of... View full abstract»

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  • Pad minimization for planar routing of multiple power nets

    Publication Year: 1990, Page(s):419 - 426
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (724 KB)

    The problem of minimizing the number of power pads, in order to guarantee the existence of a planar routing of multiple power nets, is discussed. A general lower bound is derived, and a heuristic for the general problem is discussed. Several important special cases, including the case of three power nets, are examined, and optimal strategies for pad placement are presented. It is also shown that t... View full abstract»

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  • An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel

    Publication Year: 1990, Page(s):427 - 438
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (784 KB)

    The aliasing probabilities of multiple-input signature registers (MISR) with m inputs for a 2m-ary symmetric channel, where each of the (2m-1) possible errors is equally likely, are analyzed. For this error model, the aliasing probabilities of MISRs are analyzed using the weight distributions of maximum-distance-separable (MDS) codes. The results show that the aliasi... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu