IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • Jan 1990

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Displaying Results 1 - 10 of 10
  • Fast effective heuristics for the graph bisectioning problem

    Publication Year: 1990, Page(s):91 - 98
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    The graph bisectioning problem has several applications in VLSI layout, such as floorplanning and module placement. A sufficient condition for optimality of a given bisection is presented. This condition leads to an algorithm that always finds an optimal bisection for a certain class of graphs. A greedy approach is then used to develop a more powerful heuristic. On small random graphs with up to 2... View full abstract»

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  • Tailor: a layout system based on trapezoidal corner stitching

    Publication Year: 1990, Page(s):66 - 90
    Cited by:  Papers (31)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2400 KB)

    A VLSI layout design system named Tailor is described. Tailor operates on hierarchical layouts containing 45° multiple angles. It consists of a well-integrated set of tools, including a window-driven editor, an incremental design rule checker, a circuit extractor, a one-dimensional compactor, a channel-based global router, and a transistor size optimizer. All tools use the same user interface ... View full abstract»

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  • SMALS: a novel database for two-dimensional object location

    Publication Year: 1990, Page(s):57 - 65
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    A database called SMALS, for storage minimizing automatic level sifting, that minimizes memory requirements and query response time for object location in 2-space is discussed. Memory usage is minimized through object insertion and deletion algorithms that allocate and deallocate the database memory dynamically, obviating the need for garbage collection. A fixed-level multidensity mesh representat... View full abstract»

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  • The excess capacitance of a microstrip via in a dielectric substrate

    Publication Year: 1990, Page(s):48 - 56
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The equivalent circuit of a via that connects two semi-infinite microstrip transmission lines imbedded in a dielectric medium above a ground plane is considered. The T-type equivalent circuit consists of an excess capacitance and an excess inductance. The excess inductance of the via is the same as the one computed in the case of free space (without a substrate). The excess capacitance of the via ... View full abstract»

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  • A hardware logic simulation system

    Publication Year: 1990, Page(s):19 - 29
    Cited by:  Papers (24)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1108 KB)

    Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipeli... View full abstract»

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  • A ULSI 2-D capacitance simulator for complex structures based on actual processes

    Publication Year: 1990, Page(s):39 - 47
    Cited by:  Papers (21)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    A two-dimensional (2-D) capacitance simulator for ultra-large-scale integrated (ULSI) circuits using an improved boundary-element method (BEM) is described. The capacitance simulator was linked with a topography/process simulator to estimate the distributed capacitances of complex structures based on actual processes. The utilization of a linear discontinuous element as the shape function is propo... View full abstract»

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  • Irredundant sequential machines via optimal logic synthesis

    Publication Year: 1990, Page(s):8 - 18
    Cited by:  Papers (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state transition graph description involves the steps of state minimization, state assignment, and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and const... View full abstract»

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  • A first-order charge conserving MOS capacitance model

    Publication Year: 1990, Page(s):99 - 108
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    The Meyer capacitance model (see RCA Rev., vol.32, p.42-63, 1971) fails to obey the charge conservation law. It is shown that the charge nonconservation in the Meyer model is not due to any physical assumptions. Rather, it is caused by the mathematical error of characterizing a multidimensional function (the stored charge on the four terminals of a MOSFET) by an incomplete subset of its partial de... View full abstract»

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  • Device model approximation using 2N trees

    Publication Year: 1990, Page(s):30 - 38
    Cited by:  Papers (14)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    The application of 2N trees to device model approximation is described. The domain of the device model function is partitioned using a 2N tree, with smaller partitions where the function is more nonlinear. The function value associated with each corner of each partition is precomputed, and the function is evaluated by a given point by interpolation over the smallest partition... View full abstract»

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  • An efficient output phase assignment for PLA minimization

    Publication Year: 1990, Page(s):1 - 7
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    When a multiple-output function is realized by a PLA (programmable logic array), there is often the option of realizing either true or complementary logic for each output. The tradeoffs in implementing PLAs with and without output phase assignment are explored, and an efficient output phase assignment for PLA minimization is presented. The results of this study show that the proposed algorithm red... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu