By Topic

Electron Device Letters, IEEE

Issue 11 • Date Nov. 1999

Filter Results

Displaying Results 1 - 18 of 18
  • Improvement in the electrical properties of thin gate oxides by chemical-assisted electron stressing followed by annealing (CAESA)

    Publication Year: 1999 , Page(s): 545 - 547
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (45 KB)  

    A novel technique called chemical-assisted electron stressing followed by annealing (CAESA) is proposed to improve a thin gate oxide film's quality, After conventional oxide growth, the wafer was put into diluted HF solution (0.245%) and was current stressed in liquid with Si substrate biased negatively, It is believed the stressing current will find the local weak spots and damage them by the energy release of electrons, With additional high-temperature rapid thermal annealing (RTA), the damaged spots will be annealed out. It is found that the charge-to-breakdown Q/sub bd/ of oxide can be significantly improved by the CAESA process,. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance InGaP/InxGa/sub 1-x/As HEMT with an inverted delta-doped V-shaped channel structure

    Publication Year: 1999 , Page(s): 548 - 550
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB)  

    This letter reports a new and high-performance InGaP/In/sub x/Ga/sub 1-x/As high electron mobility transistor (HEMT) with an inverted delta-doped V-shaped channel. Due to the presence of V-shaped inverted delta-doped InGaP/In/sub x/Ga/sub 1-x/As structure, good carrier confinement and a flat and wide transconductance operation regime are expected. Experimentally, the fabricated device (1×100 μm2) shows a high gate-to-drain breakdown voltage of 30 V and a high output drain saturation current density of 826 mA/mm at V/sub GS/=2.5 V. The high transconductance expands over a very broad operation range with the maximum value of 201 mS/mm at 300 K. Meanwhile, the studied device exhibits a good microwave frequency linearity. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Very high gain millimeter-wave InAlAs/InGaAs/GaAs metamorphic HEMT's

    Publication Year: 1999 , Page(s): 551 - 553
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (70 KB)  

    We report the first demonstration of W-band metamorphic HEMTs/LNA MMICs using an AlGaAsSb lattice strain relief buffer layer on a GaAs substrate. 0.1×50 μm low-noise devices have shown typical extrinsic transconductance of 850 mS/mm with high maximum drain current of 700 mA/mm and gate-drain breakdown voltage of 4.5 V. Small-signal S-parameter measurements performed on the 0.1-μm devices exhibited an excellent fT of 225 GHz and maximum stable gain (MSG) of 12.9 dB at 60 GHz and 10.4 dB at 110 GHz. The three-stage W-band LNA MMIC exhibits 4.2 dB noise figure with 18 dB gain at 82 GHz and 4.8 dB noise figure with 14 dB gain at 89 GHz, The gain and noise performance of the metamorphic HEMT technology is very close to that of the InP-based HEMT. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance dependence of InGaP/InGaAs/GaAs pHEMTs on gate metallization

    Publication Year: 1999 , Page(s): 554 - 556
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (53 KB)  

    The performance of InGaP-based pHEMTs as a function of gate metallization is examined for Mo/Au, Ti/Au, and Pt/Au gates. DC and microwave performance of pHEMT's with 0.7-μm gate lengths is evaluated. Transconductance, threshold voltage, fT, and fmax are found to depend strongly on gate metallization. High-speed performance is achieved, with fT of 41.3 GHz and fmax of 101 GHz using Mo/Au gates. The difference in performance between devices with different gate metallizations is postulated to be due to a combination of the difference in Schottky barrier heights and different gate-to-channel spacings due to penetration of the gate metal into the InGaP barrier layer. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurately modeling the drain to source current in recessed gate P-HEMT devices

    Publication Year: 1999 , Page(s): 557 - 559
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (78 KB)  

    In this work, a continuous nonlinear model for the I/sub ds/ current source in recessed gate pseudomorphic HEMT heterostructures is proposed. A careful characterization of the DC, pulsed, and small-signal nonlinear distortion behaviour of this predominant nonlinearity has been employed in order to extract the model parameters. Being able to reproduce the current-voltage (I-V) behaviour as well as the higher order derivatives of the transconductance and output conductance, the equation is valid for an accurate control of the critical nonlinear distortion phenomena in HEMT applications. Comparisons between measured and simulated results prove its validity under both static and dynamic conditions for either large- or small-signal operation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A polycrystalline silicon thin-film transistor with a thin amorphous buffer

    Publication Year: 1999 , Page(s): 560 - 562
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (67 KB)  

    We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm2/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Corner-parasitics-free low-cost trench isolation

    Publication Year: 1999 , Page(s): 563 - 565
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (113 KB)  

    In this work, we present results on a novel low-cost, corner-parasitics-free trench isolation process. Regarding process complexity, this approach is almost as simple as LOGOS isolation, since the isolation oxide is deposited selectively within the trench. Due to the self-planarizing nature of the fill oxide, the global planarization sequence is largely simplified. With respect to scalability, this approach offers all the advantages of trench isolation with its abrupt transition of active area to isolation. However, in contrast to previous trench isolation schemes, corner-parasitic effects are eliminated by means of the extended trench isolation gate technology (EXTIGATE) device geometry. As a result, excellent narrow width characteristics and subthreshold curves without kink effect are obtained. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reverse short-channel effect in metal-induced laterally crystallized polysilicon thin-film transistors

    Publication Year: 1999 , Page(s): 566 - 568
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (44 KB)  

    A reverse short-channel effect, manifested by an increase in the transistor threshold voltage as the channel length is reduced, is observed in conventional metal-induced laterally crystallized thin-film transistors. Such an effect has not been observed in regular solid phase crystallized thin-film transistors and can be eliminated by a brief hydrogen plasma treatment. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel ultrathin elevated channel low-temperature poly-Si TFT

    Publication Year: 1999 , Page(s): 569 - 571
    Cited by:  Papers (48)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (52 KB)  

    A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 /spl Aring/) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V/sub ds/=30 V, V/sub gs/=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFT's. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improvement of junction leakage of nickel silicided junction by a Ti-capping layer

    Publication Year: 1999 , Page(s): 572 - 573
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (41 KB)  

    A novel NiSi process with a thin Ti-cap layer is proposed, for the first time, to improve the leakage problem of Ni-silicided junction. The Ti-cap samples exhibit a very low leakage current density about 1/spl times/10/sup -9/ A/cm/sup 2/ after 600/spl deg/C annealing, which is one order of magnitude reduction comparing with uncapped samples. From Auger analyzes, it is found that this significant improvement results from suppression of the oxidation of the Ni-silicide during the thermal annealing process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-mobility poly-Si TFTs fabricated on flexible stainless-steel substrates

    Publication Year: 1999 , Page(s): 574 - 576
    Cited by:  Papers (20)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (98 KB)  

    High mobility polycrystalline Si thin-film transistors (poly-Si TFTs) are firstly fabricated on flexible stainless-steel substrates 100 μm thick through low-temperature processes where both active Si and gate SiO2 films are deposited by glow-discharge sputtering and the Si films are crystallized by KrF excimer laser irradiation. The gate SiO2 films are sputter-deposited in oxygen atmosphere from the SiO2 target. Resulting poly-Si TFTs show excellent characteristics of mobility of 106 cm2/V/spl middot/s and drain current on-off ratio of as high as 1×106. Thus, the poly-Si TFTs are very promising for realizing novel flat panel displays of lightweight and rugged LCDs and LEDs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simulated turn-off of 4H-SiC gate turn-off thyristors with gate electrodes on the p-base or the n-base

    Publication Year: 1999 , Page(s): 577 - 579
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB)  

    Turn-off simulations of a 4H-SiC GTO thyristor structure having a gated p-base and p-type substrate are compared with that having a gated n-base and n-type substrate. Two gate drive circuits are considered, one with a voltage source and resistor between the gate and adjacent emitter region, and the other with a voltage source and resistor between the gate and farthest emitter region. The gated n-base thyristor's substrate current increases atypically before the device turns off. Also, the gated n-base structure turns off when the gate circuit is connected directly to the emitter region furthest from the gate region, but the gated p-base structure does not. Furthermore, turn-off gain is lower for the gated n-base structure due to mobility differences as demonstrated by current-voltage (I-V) and current versus time (I-t) curves. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel gate geometry for the IGBT: the trench planar insulated gate bipolar transistor (TPIGBT)

    Publication Year: 1999 , Page(s): 580 - 582
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB)  

    This letter demonstrates a simple way to improve the performance of a planar, fine lithography insulated gate bipolar transistor (IGBT), by incorporating a trench gate between the cathode cells. The results of this new trench-planar IGBT (TPIGBT) clearly demonstrate a significant reduction in the voltage drop without degrading the breakdown voltage. The switching analysis indicates that the TPIGBT represents a good trade-off between planar and trench structures. By separating the trench gate requirements away from the cathode cells, the technology development cycle and costs can be reduced. Furthermore, the reduced cell-width and the shallow trench presents TPIGBT as a cost-effective structure for high-voltage applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-speed silicon single-electron random access memory

    Publication Year: 1999 , Page(s): 583 - 585
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB)  

    A silicon random access memory using a single-electron tunnelling transistor (SETT) in the form of a multiple tunnel junction (MTJ) in a silicon nanowire has been assessed in terms of its write speed, retention time, and selectivity at an operating temperature of 4.2 K. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Role of hole fluence in gate oxide breakdown

    Publication Year: 1999 , Page(s): 586 - 588
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB)  

    A simple model which links the primary hole and Fowler-Nordheim (FN) electron injections to oxide breakdown is established and the calculation based on this model is in good agreement with our experiments. When the sum of the active trap density D/sup pri/ due to primary hole injection and the active trap density D/sup n/ due to FN electron injection reaches a critical value D/sub cri/, the oxide breaks down. The hole is two orders of magnitude more effective than FN electron in causing breakdown. These new findings are imperative in predicting oxide reliability and device lifetime. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Spreading-resistance temperature sensor on silicon-on-insulator

    Publication Year: 1999 , Page(s): 589 - 591
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (42 KB)  

    A spreading-resistance temperature (SRT) sensor is fabricated on silicon-on-insulator (SOI) substrate and achieves promising characteristics as compared with similar SRT sensor on bulk silicon wafers. Moreover, experimental results show that the maximum operating temperature of thin-film (1.2 μm) SOI SRT sensor can reach 450/spl deg/C, much higher than 350/spl deg/C of thick-film (10 μm) SOI SRT sensor under the same current level. With complete oxide isolation, this sensor structure can be potentially used in low power integrated sensors operating at temperatures as high as 450/spl deg/C. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • In situ-doped amorphous Si/sub 0.8/C/sub 0.2/ emitter bipolar transistors

    Publication Year: 1999 , Page(s): 592 - 594
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (53 KB)  

    The fabrication and characterization of in situ-doped amorphous Si/sub 0.8/C/sub 0.2/ emitter transistors are presented. Emitter Gummel numbers exceeding 10/sup 14/ s/cm/sup 4/ are reported for the first time in this type of structure. The high values obtained for G/sub E/ are believed to be due to the valance band discontinuity between the Si/sub 0.8/C/sub 0.2/ layer and the crystalline part of the emitter, which effectively blocks the minority carrier injection from the base into the noncrystalline part of the emitter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evidence of substrate enhanced high-energy tails in the distribution function of deep submicron MOSFETs by light emission measurements

    Publication Year: 1999 , Page(s): 595 - 597
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (69 KB)  

    This letter reports direct experimental evidence that the high-energy tail of the hot carrier luminescence distribution of deep submicron silicon MOSFETs is essentially modified by the application of a substrate voltage. The bias and temperature dependence of the phenomenon are consistent with an enhancement of the high-energy tail of the energy distribution due to a second impact ionization event occurring at the drain to substrate junction. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Amitava Chatterjee