IEEE Transactions on Computers

Issue 9 • Sept. 1999

Filter Results

Displaying Results 1 - 11 of 11
  • Concurrent event handling through multithreading

    Publication Year: 1999, Page(s):903 - 916
    Cited by:  Papers (11)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (283 KB)

    Exceptions have traditionally been used to handle infrequently occurring and unpredictable events during normal program execution. Current trends in microprocessor and operating systems design continue to increase the cost of event handling. Because of the deep pipelines and wide out-of-order superscalar architectures of contemporary microprocessors, an event may need to nullify a large number of ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Circuit optimization by rewiring

    Publication Year: 1999, Page(s):962 - 970
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (623 KB)

    Presents a very efficient optimization method suitable for multi-level combinational circuits. The optimization is based on incremental restructuring of a circuit through a sequence of additions and removals of redundant wires. Our algorithm applies the techniques of automatic test pattern generation (ATPG), which can efficiently detect redundancies. During the ATPG process, certain nodes in the c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The superthreaded processor architecture

    Publication Year: 1999, Page(s):881 - 902
    Cited by:  Papers (47)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism that is available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism that are available in general-purpose application programs. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A chip-multiprocessor architecture with speculative multithreading

    Publication Year: 1999, Page(s):866 - 880
    Cited by:  Papers (107)  |  Patents (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Much emphasis is now being placed on chip-multiprocessor (CMP) architectures for exploiting thread-level parallelism in applications. In such architectures, speculation may be employed to execute applications that cannot be parallelized statically. In this paper, we present an efficient CMP architecture for the speculative execution of sequential binaries without source recompilation. We present s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An effective built-in self-test scheme for parallel multipliers

    Publication Year: 1999, Page(s):936 - 950
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    An effective built-in self-test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed very high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using traffic regulation to meet end-to-end deadlines in ATM networks

    Publication Year: 1999, Page(s):917 - 935
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Considers the support of hard real-time connections in ATM networks. In an ATM network, a set of hard real-time connections can be admitted only if the worst-case end-to-end delays of cells belonging to individual connections are less than their deadlines. There are several approaches to managing the network resources in order to meet the delay requirements of connections. This paper focuses on th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel implementation of multidimensional transforms without interprocessor communication

    Publication Year: 1999, Page(s):951 - 960
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Presents a modular algorithm which is suitable for computing a large class of multidimensional transforms in a general-purpose parallel environment without interprocessor communication. Since it is based on matrix-vector multiplication, it does not impose restrictions on the size of the input data as many existing algorithms do. The method is fully general, since it does not depend on the specific... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ordered binary decision diagrams and minimal trellises

    Publication Year: 1999, Page(s):971 - 986
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Ordered binary decision diagrams (OBDDs) are graph-based data structures for representing Boolean functions. They have found widespread use in computer-aided design and in formal verification of digital circuits. Minimal trellises are graphical representations of error-correcting codes that play a prominent role in coding theory. This paper establishes a close connection between these two graphica... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pseudo-Kronecker expressions for symmetric functions

    Publication Year: 1999, Page(s):987 - 990
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Pseudo-Kronecker Expressions (PSDKROs) are a class of AND/EXOR expressions. In this paper, it is proven that exact minimization of PSDKROs for totally symmetric functions can be performed in polynomial time. A new implementation method for PSDKROs is presented. Experimental results are given to show the efficiency of the presented approach in comparison to previously published work on AND/EXOR min... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast linearly independent arithmetic expansions

    Publication Year: 1999, Page(s):991 - 999
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    The concept of Linearly Independent arithmetic (LIA) transforms and expansions is introduced in this paper. The recursive ways of generating forward and inverse fast transforms for LIA are presented. The paper describes basic properties and lists those LIA transforms which have convenient fast forward algorithms and easily defined inverse transforms. In addition, those transforms which require hor... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Partial scan with preselected scan signals

    Publication Year: 1999, Page(s):1000 - 1005
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    This paper deals with partial scan approaches that select scan signals oblivious to the availability of flip-flops (FFs). Such approaches can greatly reduce the number of scan signals since maximum freedom is presented when selecting signals. However, to actually scan the selected signals, one must make them drive FFs. We study the problem of replicating and retiming a circuit to make a set of sca... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org