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Electron Device Letters, IEEE

Issue 10 • Date Oct. 1999

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Displaying Results 1 - 15 of 15
  • Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

    Publication Year: 1999 , Page(s): 498 - 500
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (67 KB)  

    The channel width dependence of gate delay in 0.18-μm CMOSFET has been characterized. Substantial increase of gate delay observed in the narrow channel width region is found due to channel width independent capacitance components, which is inherent to transistors. An expression for gate delay considering the channel width independent capacitance components and gate sheet resistance is derived and compared with experimental data. The minimum gate delay is shown to result from the compromise between delay components proportional to channel width and proportional to inverse of channel width. Although the channel width independent capacitance is negligible in the wide channel width region, the gate delay of the 1-μm channel width ring oscillator increased more than 20% compared with the 5-μm channel width ring oscillator. View full abstract»

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  • Improved hot-electron reliability in high-performance, multilevel-metal CMOS using deuterated barrier-nitride processing

    Publication Year: 1999 , Page(s): 501 - 503
    Cited by:  Papers (7)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (54 KB)  

    Deuterated barrier-nitride films and anneals in a deuterium ambient prior to first-metal have been incorporated into a conventional high-performance CMOS process and subjected to subsequent processing through five levels of metal. Device hot-electron stress results confirm that, even though some initial relaxation of the transistor lifetime improvement is observed with further hot processing, significant lifetime improvement can be achieved through full wafer processing through five levels of metal. The barrier-nitride acts as a reservoir for deuterium, maintaining high concentrations in the device regions through further processing. These results support the efficacy of using a deuterium reservoir to achieve a hot-electron hardened transistor. View full abstract»

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  • Analysis of capacitor breakdown mechanisms due to crystal-originated pits

    Publication Year: 1999 , Page(s): 504 - 506
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (98 KB)  

    The extent to which crystal originated defect pits (COPs) will enhance capacitor B-mode failures has been examined as a function of substrate carrier type/dopant concentration and bias mode (accumulation/inversion). An unexpected immunity to COPs, found for n-type capacitors biased into accumulation, could be readily explained by invoking Fowler-Nordheim (FN) tunneling variations due to the morphology of the capacitor electrodes, as revealed by cross-sectional TEM on simulated COPs formed by KOH anisotropic etching. View full abstract»

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  • Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

    Publication Year: 1999 , Page(s): 507 - 509
    Cited by:  Papers (2)  |  Patents (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (49 KB)  

    In/sub 0.5/Al/sub 0.5/As/In/sub 0.5/Ga/sub 0.5/As HEMTs have been grown metamorphically on GaAs substrates oriented 6/spl deg/ off [100] toward [111]A using a graded InAlAs buffer. The devices are enhancement mode and show good dc and RF performance. The 0.6-μm gate length devices have saturation currents of 262 mA/mm at a gate bias of 0.7 V and a peak transconductance of 647 mS/mm. The 0.6 μm×3 mm devices tested on-wafer have output powers up to 30 mW/mm and 46% power-added-efficiency (PAE) at 1 V drain bias and 850 MHz. When biased and matched for best efficiency performance, this same device has up to 68% PAE at V/sub d/=1 V. View full abstract»

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  • A novel InP/InAlGaAs negative-differential-resistance heterojunction bipolar transistor (NDR-HBT) with interesting topee-shaped current-voltage characteristics

    Publication Year: 1999 , Page(s): 510 - 513
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB)  

    A new and interesting negative-differential-resistance heterojunction bipolar transistor (NDR-HBT) based on the InP/InAlGaAs material system is fabricated successfully and demonstrated. Due to the employment of narrow base and /spl delta/-doped sheet at the emitter-base (E-B) heterojunction, the significant and interesting topee-shaped current-voltage (I-V) characteristics are observed in the low current regime. A peak-to-valley current ratio (PVCR) up to 11 in the NDR loci is found. In the higher current regimes, on the other hand, NDR phenomena disappear and the device acts as a normal bipolar transistor. These interesting properties are believed to be attributed mainly to the modulation of potential spike resulting from the specified device structure. View full abstract»

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  • p-Type SiGe transistors with low gate leakage using SiN gate dielectric

    Publication Year: 1999 , Page(s): 514 - 516
    Cited by:  Papers (2)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (79 KB)  

    Using high-quality jet-vapor-deposited (JVD) SiN as gate dielectric, p-type SiGe transistors are fabricated on SiGe heterostructures grown by ultra-high-vacuum chemical vapor deposition (UHVCVD). For an 0.25-μm gate-length device, the gate leakage current is as small as 2.4 nA/mm at V/sub ds/=-1.0 V and V/sub gn/=0.4 V. A maximum extrinsic transconductance of 167 mS/mm is measured. A unity current gain cutoff frequency of 27 GHz and a maximum oscillation frequency of 35 GHz are obtained. View full abstract»

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  • Pseudomorphic InP HEMTs with dry-etched source vias having 190 mW output power and 40% PAE at V-band

    Publication Year: 1999 , Page(s): 517 - 519
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (91 KB)  

    We report state-of-the-art V-band power performance of 0.15-μm gate length InGaAs/InAlAs/InP HEMT's which have 15 μm×23 μm dry-etched through-substrate source vias (substrate thickness 50 μm). The 500-μm wide InP HEMT's were measured in fixture at 60 GHz and demonstrated an output power of 190 mW with 40% power-added efficiency (PAE) and 6.8 dB power gain at an input power of 16 dBm. These results represent the best combination of power and PAE reported to date at this frequency for any solid state device. The results are achieved through optimization of the InP-based heterostructure which incorporates a graded pseudomorphic InGaAs channel and a graded pseudomorphic InAlAs Schottky barrier layer, and the use of 15 μm×23 μm dry-etched through-substrate source vias. View full abstract»

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  • Enhanced low-temperature corner current-carrying inherent to shallow trench isolation (STI)

    Publication Year: 1999 , Page(s): 520 - 522
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (69 KB)  

    The subthreshold hump in the current-voltage (I-V) characteristics caused by the current-carrying corner in shallow-trench-isolated (STI) n-channel MOSFET's is significantly enhanced at reduced temperatures. Numerical simulations show that the sensitivity of the corner channel's threshold voltage to temperature is smaller than that of the center channel's threshold voltage. This, together with the reduced subthreshold swing at low temperatures, contribute to an enhanced subthreshold hump, and is potentially important for emerging cryogenic applications. View full abstract»

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  • Cell-based analytic statistical model with correlated parameters for intrinsic breakdown of ultrathin oxides

    Publication Year: 1999 , Page(s): 523 - 525
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (79 KB)  

    The cell-based analytic statistical model, with the cell area A/sub O/ and the critical trap number per cell n/sub BD/ both as parameters, is one of the widely cited literature models in calculating the critical density of neutral electron traps that trigger the intrinsic breakdown of ultrathin oxides. This letter reports a new correlation between A/sub O/ and n/sub BD/, which can effectively reduce the cell-based model to one with the only fitting parameter n/sub BD/. Reproduction of charge-to-breakdown data has shown that (1) n/sub BD/ decreases for reduced oxide thicknesses and (2) the range of intrinsic breakdown is relatively narrowed for increasing areas. The work also addresses the ultimate thickness limit for breakdown, as set critically at n/sub BD/=1. View full abstract»

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  • Adaptive-learning neuron integrated circuits using metal-ferroelectric (SrBi/sub 2/Ta/sub 2/O/sub 9/)-semiconductor (MFS) FET's

    Publication Year: 1999 , Page(s): 526 - 528
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (195 KB)  

    An adaptive-learning neuron circuit was fabricated for the first time by integrating a metal-ferroelectric-semiconductor (MFS) FET and a complementary unijunction transistor (CUJT) on a silicon-on-insulator (SOI) structure. SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) was selected as a ferroelectric gate material and it was deposited by liquid source misted chemical deposition (LSMCD) method. In fabrication of the circuit, a new selective etchant, NH/sub 4/F:HCl, was used to remove the unnecessary SBT film, since it was found from preliminary experiments that the parasitic ferroelectric capacitors prevented normal operation of the circuit. It was found that the drain current of the MFSFET was changed gradually by applying a number of input pulses with a sufficiently short duration time of 20 ns. The gradual change in the output pulse frequency of the neuron circuit was also demonstrated as the number of input pulses was increased. View full abstract»

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  • Three-terminal silicon surface junction tunneling device for room temperature operation

    Publication Year: 1999 , Page(s): 529 - 531
    Cited by:  Papers (22)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (73 KB)  

    This letter reports excellent negative differential conductance (NDC) characteristics at room temperature in a three-terminal silicon surface junction tunneling (Si SJT) device, with the peak-to-valley current ratio of more than two. The tunneling device was fabricated on a SIMOX wafer to achieve an extremely small bulk leakage current together with a sharp drain impurity profile. In addition, a ring-shaped gate structure was employed to eliminate the effect of the field oxide corner, resulting in the significant reduction of an excess tunneling current at the tunneling junction. As a simple circuit demonstration, gate-controlled latch characteristics are also shown, which cannot be easily achieved by a two-terminal tunneling device. View full abstract»

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  • Low-frequency noise properties of dynamic-threshold (DT) MOSFET's

    Publication Year: 1999 , Page(s): 532 - 534
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (74 KB)  

    This paper shows that MOSFET operated in dynamic-threshold (DT) mode (V/sub body/=V/sub gate/) is more suitable for low-noise RF/analog applications than those operated in conventional mode (V/sub body/=V/sub source/). Detailed low-frequency noise properties of these two modes of device operation were compared for 0.31-μm gate MOSFET's, in which NMOS's are surface-channel devices (S.C.) and PMOS's are buried-channel (B.C.) devices. Experimental data show that when the devices are biased at same transconductance, the low-frequency noise in DT mode is 30 times lower (at g/sub m/=2.2×10/sup -3/ S) than that in the conventional mode for the B.C. devices and ten times (at g/sub m/=2.0×10/sup -3/ S) lower for the S.C. devices. View full abstract»

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  • Suppression of boron penetration for p/sup +/ stacked poly-Si gates by using inductively coupled N2 plasma treatment

    Publication Year: 1999 , Page(s): 535 - 537
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (79 KB)  

    Nitridation of stacked poly-Si gates by inductively coupled N/sub 2/ plasma (ICNP) treatment has been shown to suppress boron penetration and improve gate oxide integrity. The ICNP treatments on the stacked poly-Si layers create nitrogen-rich layers not only between the stacked poly-Si layers but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. In addition, positioning of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and improvement of gate oxide reliability. View full abstract»

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  • Exploration of velocity overshoot in a high-performance deep sub-0.1-μm SOI MOSFET with asymmetric channel profile

    Publication Year: 1999 , Page(s): 538 - 540
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (66 KB)  

    The electron velocity overshoot phenomenon in the inversion layer is experimentally investigated using a novel thin-film silicon-on-insulator (SOI) test structure with channel lengths down to 0.08 μm. The uniformity of the carrier density and tangential field is realized by employing a lateral asymmetric channel (LAC) profile. The electron drift velocity observed in this work is 9.5×106 cm/s for a device with L/sub eff/=0.08 μm at 300 K. The upward trend in electron velocity can be clearly noticed for decreasing channel lengths. View full abstract»

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  • Corrections to "High-field electron velocity in silicon surface-accumulation layer"

    Publication Year: 1999 , Page(s): 541
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7 KB)  

    In the above-named work, there were two editorial errors. On p. 491, left column, the first full sentence should read "An application of a substrate bias voltage Vsub provides a desired degree of band bending at the back Si??SiO2 interface." On p. 491, the first sentence in the right column should read "For the large-parallel-field case [Fig. 2(b)], the drain voltage was provided by voltage pulses of 1 μs duration and 0.1% duty cycle to minimize the effect of self-heating." View full abstract»

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