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Electron Device Letters, IEEE

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Electron Device Letters, IEEE

Issue 10 • Date Oct. 1999

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Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

Improved hot-electron reliability in high-performance, multilevel-metal CMOS using deuterated barrier-nitride processing

Analysis of capacitor breakdown mechanisms due to crystal-originated pits

Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

A novel InP/InAlGaAs negative-differential-resistance heterojunction bipolar transistor (NDR-HBT) with interesting topee-shaped current-voltage characteristics

p-Type SiGe transistors with low gate leakage using SiN gate dielectric

Pseudomorphic InP HEMTs with dry-etched source vias having 190 mW output power and 40% PAE at V-band

Enhanced low-temperature corner current-carrying inherent to shallow trench isolation (STI)

Cell-based analytic statistical model with correlated parameters for intrinsic breakdown of ultrathin oxides

Adaptive-learning neuron integrated circuits using metal-ferroelectric (SrBi/sub 2/Ta/sub 2/O/sub 9/)-semiconductor (MFS) FET's

Three-terminal silicon surface junction tunneling device for room temperature operation

Low-frequency noise properties of dynamic-threshold (DT) MOSFET's

Suppression of boron penetration for p/sup +/ stacked poly-Si gates by using inductively coupled N₂ plasma treatment

Exploration of velocity overshoot in a high-performance deep sub-0.1-μm SOI MOSFET with asymmetric channel profile

Corrections to "High-field electron velocity in silicon surface-accumulation layer"

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