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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Oct. 1999

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Displaying Results 1 - 13 of 13
  • Corrections to "MOGAC: A multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems"

    Publication Year: 1999, Page(s): 1527
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (150 KB)

    In the above-named article [ibid., vol. 16, pp. 920??935, Oct. 1998] there is an error in the experimental results reported for the Hou 3&4 (clustered) benchmark, due to a typographical error in its task collection input file. The last line of the The Hou 3&4 (clustered) row of Table IV on page 932 of the original article should be replaced with Table I of this short paper. For this example, avera... View full abstract»

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  • Extension of the VR discretization scheme for velocity saturation

    Publication Year: 1999, Page(s):1508 - 1511
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (124 KB)

    It is argued that the vector resolution discretization scheme is not consistent with the velocity saturation model. As a result, the simulation results show dependence on grid orientation. A modification is then presented to overcome this difficulty. Simulation examples are discussed to clearly demonstrate the improvement obtained with the new scheme. Finally, some comments are made regarding the ... View full abstract»

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  • Controller-based power management for control-flow intensive designs

    Publication Year: 1999, Page(s):1496 - 1508
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    This paper presents a low-overhead controller-based power management technique that redesigns control logic to reconfigure the existing data path components under idle conditions so as to minimize unnecessary activity. Controller-based power management exploits the fact that though the control signals in a register-transfer level implementation are fully specified, they can be respecified under ce... View full abstract»

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  • Fault emulation: A new methodology for fault grading

    Publication Year: 1999, Page(s):1487 - 1495
    Cited by:  Papers (56)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    In this paper, we introduce a method that uses the field programmable gate array (FPGA)-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the performance of fault grading, which is one of the most time consuming tasks in the circuit design and test process. We employ a serial fault emulation algorithm enhanced by two sp... View full abstract»

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  • Efficient extra material critical area algorithms

    Publication Year: 1999, Page(s):1480 - 1486
    Cited by:  Papers (14)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a ... View full abstract»

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  • Average-case technology mapping of asynchronous burst-mode circuits

    Publication Year: 1999, Page(s):1418 - 1434
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    This paper presents a technology mapper that optimizes the average performance of asynchronous burst-mode control circuits. More specifically, the mapper can be directed to minimize either the average latency or the average cycle time of the circuit. The input to the mapper is a burst-mode specification and its NAND-decomposed unmapped network. The mapper preprocesses the circuit's specification u... View full abstract»

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  • An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering

    Publication Year: 1999, Page(s):1519 - 1526
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Because definition of L-shaped channels in a floorplan graph breaks all the cyclic precedence constraints in a building block layout, routing space in a layout can be fully separated and defined as straight and L-shaped channels to guarantee a safe routing ordering. However, L-shaped channel routing is more difficult than straight channel routing. Hence, it is necessary for the completion of detai... View full abstract»

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  • Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic

    Publication Year: 1999, Page(s):1442 - 1451
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB)

    We present a chip-level global router based on a new, more accurate global routing model for the multilayer macro-cell (building block) technology. The routing model uses a three-dimensional mixed directed/undirected routing graph, which provides not only the topological information but also the layer information. The irregular routing graph closely models the multilayer routing problem, so the gl... View full abstract»

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  • A gridless multilayer router for standard cell circuits using CTM cells

    Publication Year: 1999, Page(s):1462 - 1479
    Cited by:  Papers (5)  |  Patents (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2076 KB)

    We present a gridless multilayer router suitable for standard cell circuits using central terminal model (CTM) cells. A CTM cell has pins in the middle which split the over-the-cell (OTC) routing region into top and bottom parts. Nets are routed in both the channel (if needed) and OTC by using a channel router. Our router uses a combined constraint graph and tile expansion algorithm. We report the... View full abstract»

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  • Hardware/software co-synthesis with memory hierarchies

    Publication Year: 1999, Page(s):1405 - 1417
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    This paper introduces the first hardware/software co-synthesis algorithm of distributed real-time systems that optimizes the memory hierarchy along with the rest of the architecture. Memory hierarchies (caches) are essential for modern embedded cores to obtain high performance. They also represents a significant portion of the cost, size and power consumption of many embedded systems. Our algorith... View full abstract»

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  • Interconnection analysis for standard cell layouts

    Publication Year: 1999, Page(s):1512 - 1519
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    We present an accurate model and procedures for predicting the common physical design characteristics of standard cell layouts (i.e., the interconnection length and the chip area). The predicted results are obtained from analysis of the net list only, that is, no prior knowledge of the functionality of the design is used. Random and optimized placements, global routing, and detailed routing are ea... View full abstract»

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  • An integral equation of the second kind for computation of capacitance

    Publication Year: 1999, Page(s):1435 - 1441
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    We report a new formulation for computing the charge density of a multiconductor system in a homogeneous or multiple dielectric medium. The technique employs single-layer potential description to yield a Fredholm integral equation of the second kind, for which efficient numerical algorithms are available. Furthermore, the associated discretization matrix has improved conditioning. Here, we conside... View full abstract»

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  • Multilayer pin assignment for macro cell circuits

    Publication Year: 1999, Page(s):1452 - 1461
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    We present a multilayer pin (crossing point) assignment algorithm for macro cell circuits. The pin-assignment algorithm takes advantage of a multilayer chip-level global router that we recently developed. Previously reported methods also sought to combine global routing and pin assignment, but their models forced them to use inferior global routing methods. No previous pin-assignment program can h... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu