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IEEE Transactions on Computers

Issue 2 • Date Feb. 1990

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Displaying Results 1 - 17 of 17
  • Comments on "Signature analysis for multiple output circuits" by R. David

    Publication Year: 1990, Page(s):287 - 288
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    The probability of a fault-free signature has been calculated in the above-named paper (see ibid., vol.C-35, no.9, p.830-7 (1986)) and in an earlier paper by the same author (see ibid., vol.C-29, no.7, p.668-73 (1980)). Implicitly, it was considered as the probability of masking due to signature analysis. It is shown here that this does not correspond exactly to the probability of aliasing. A new ... View full abstract»

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  • Correction to 'Representational and denotational semantics of digital systems'

    Publication Year: 1990
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (79 KB)

    Three errors are corrected which appeared in a paper by the author (see ibid., vol.38, no.7, p.986-99 (1989)). The corrections relate to variable bindings in quantification and lambda abstraction, the notation for subranges of the integers, and the definition of monotonicity (in Section V).<> View full abstract»

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  • Network resilience: a measure of network fault tolerance

    Publication Year: 1990, Page(s):174 - 181
    Cited by:  Papers (38)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    A probabilistic measure of network fault tolerance expressed as the probability of a disconnection is proposed. Qualitative evaluation of this measure is presented. As expected, the single-node disconnection probability is the dominant factor irrespective of the topology under consideration. The authors derive an analytical approximation to the disconnection probability and verify it with a Monte ... View full abstract»

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  • Algorithms for image component labeling on SIMD mesh-connected computers

    Publication Year: 1990, Page(s):276 - 281
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Two parallel algorithms are presented for the problem of labeling the connected components of a binary image. The machine model is an SIMD two-dimensional mesh-connected computer consisting of an N×N array of processing elements, each containing a single pixel of an N×N image. Both new algorithms use a local shrinking operation defined by S. Levialdi... View full abstract»

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  • Location of a faulty module in a computing system

    Publication Year: 1990, Page(s):182 - 194
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (996 KB)

    Considering the interplay between different phases of fault tolerance, a new problem of locating a faulty module in a computing system is formulated and solved. First, the probability of each module being faulty, or faulty probability, is calculated using the likelihood principle from the model parameters for fault detection, diagnostics, error propagation, and error detection. Then, based on the ... View full abstract»

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  • A spectral lower bound technique for the size of decision trees and two-level AND/OR circuits

    Publication Year: 1990, Page(s):282 - 287
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A universal lower-bound technique for the size and other implementation characteristics of an arbitrary Boolean function as a decision tree and as a two-level AND/OR circuit is derived. The technique is based on the power spectrum coefficients of the n dimensional Fourier transform of the function. The bounds vary from constant to exponential and are tight in many cases. Several examples ... View full abstract»

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  • Incremental distance and diameter sequences of a graph: new measures of network performance

    Publication Year: 1990, Page(s):230 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Two new measures of network performance, namely, the incremental distance sequence and the incremental diameter sequence, are introduced for application in network topology design. These sequences can be defined for both vertex deletions and edge deletions. A complete characterization of the vertex-deleted incremental distance sequence is presented. Proof of this characterization is constructive i... View full abstract»

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  • On the complexity of mod-2l sum PLA's

    Publication Year: 1990, Page(s):262 - 266
    Cited by:  Papers (61)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Consideration is given to the realization of logic functions by using PLAs with an exclusive-OR (EXOR) array, where a function is represented by mod-2 (EXOR) sum-of-products (ESOPs) and both true and complemented variables are used. The authors propose a new PLA structure using an EXOR array. They derive upper bounds on the number of products of this type of PLA that are useful for estimating the ... View full abstract»

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  • Performance and architectural issues for string matching

    Publication Year: 1990, Page(s):238 - 250
    Cited by:  Papers (7)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    The authors introduce special heuristics to the Knuth-Morris-Pratt algorithm to reduce the time and space required to perform the string matching. They compare their hardware-based approach to the software approaches embodied in the Unix system grep and fgrep commands. Simulation results show that the hardware approach can provide a 25-500-fold performance improvement, depending on the complexity ... View full abstract»

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  • On the design of a unidirectional systolic array for key enumeration

    Publication Year: 1990, Page(s):266 - 269
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A systolic array for enumerating keys in n keys in 3n -1 time steps is introduced. This array has unidirectional data flow and achieves the maximum data pipelining rate. Modifications of the array for solving the closest-neighbor problems in computational geometry are presented View full abstract»

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  • Extreme area-time tradeoffs in VLSI

    Publication Year: 1990, Page(s):251 - 257
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    Consideration is given to the layout of bounded fan-in and fan-out prefix computation graphs in VLSI, and it is shown that the area requirements of such graphs exhibit this interesting property. A small constant factor reduction in time of computation from 2 log η to log η increases the area required to embed an η node prefix computation graph significantly from O(η log η) to &... View full abstract»

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  • Built-in testing of integrated circuit wafers

    Publication Year: 1990, Page(s):195 - 205
    Cited by:  Papers (21)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1052 KB)

    Production testing of a digital circuit requires the generation of a sequence of tests and their application to the circuit being tested. Currently, in test application, the output of the circuit under test is compared to a known correct output for each test. The method has some drawbacks likely to become more critical in the near future. In homogeneous systems of identical integrated circuits of ... View full abstract»

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  • Synthesizing robust data structures-an introduction

    Publication Year: 1990, Page(s):161 - 173
    Cited by:  Papers (11)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1260 KB)

    A formal approach is presented for the analysis and synthesis of robust data structures. The entire data structure is viewed as a collection of data elements related via some attributes. The relationships are specified by a set of axioms in first-order logic. Faults in attributes invalidate some of the axioms. The invalidated axioms are used to detect and correct the faulty attributes. The authors... View full abstract»

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  • Fault diagnosis of RAMs from random testing experiments

    Publication Year: 1990, Page(s):220 - 229
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    It is shown how random testing experiments can be used for fault diagnosis. Starting from a prescribed set of faults, the result of the first experiment allows the authors (1) to determine a subset of faults which are compatible with this result and (2) to choose the second experiment, and so on. An algorithm (each step of which is an experiment) is given, and simulation results are presented View full abstract»

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  • Fault tolerance in linear systolic arrays using time redundancy

    Publication Year: 1990, Page(s):269 - 276
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    A linear systolic array with fault-tolerant capabilities is described. Fault tolerance is achieved by using triple time redundancy. The array is capable of undergoing reconfiguration and can operate in a gracefully degradable mode. The concept of algorithm remapping on degraded (smaller) arrays is integrated with that of graceful degradation to obtain a general fault-tolerance technique. A new tec... View full abstract»

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  • A VLSI design for computing exponentiations in GF(2m) and its application to generate pseudorandom number sequences

    Publication Year: 1990, Page(s):258 - 262
    Cited by:  Papers (28)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    A VLSI design for computing exponentiation in finite fields is developed. An algorithm to generate a relatively long pseudorandom number sequence is presented. It is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme View full abstract»

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  • Optimal dynamic remapping of data parallel computations

    Publication Year: 1990, Page(s):206 - 219
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1200 KB)

    A large class of data parallel computations is characterized by a sequence of phases, with phase changes occurring unpredictably. Dynamic remapping of the workload to processors may be required to maintain good performance. The problem considered, for which the utility of remapping and the future behavior of the workload are uncertain, arises when phases exhibit stable execution requirements durin... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org