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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Issue 9 • Date Sep 1999

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Displaying Results 1 - 15 of 15
  • Stability robustness of continuous-time perturbed descriptor systems

    Publication Year: 1999 , Page(s): 1153 - 1155
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB)  

    In this paper, the stability robustness of linear continuous-time descriptor systems with structured parameter perturbations is investigated. A new sufficient criterion is presented for ensuring that the linear continuous-time descriptor system remains regular, impulse free, and asymptotically stable under structured parameter perturbations. The presented criterion is mathematically proved to be less conservative than the existing one View full abstract»

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  • A method for identification of asymptotically stable equilibrium points of a certain class of dynamic circuits

    Publication Year: 1999 , Page(s): 1101 - 1109
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    The paper deals with nonlinear dynamic circuits driven by dc voltage and current sources. The problem considered is as follows. A class of nonlinear-resistive circuits having a unique or multiple operating points is considered. Any circuit of this class generates infinitely many dynamic circuits so that each operating point of the resistive circuit is an equilibrium point of all these dynamic circuits. Hence, the question arises as to how to identify these operating points of a given resistive circuit, which are asymptotically stable equilibrium states of any dynamic circuit belonging to an associated class, in this paper, a method is developed enabling us to solve this problem for a certain class of dynamic circuits. The method is based on analysis of the resistive circuit only. It is simple and easy for implementation. Two numerical examples illustrate the proposed approach View full abstract»

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  • A low-sensitivity programmable BJT current-mode filtering technique

    Publication Year: 1999 , Page(s): 1131 - 1134
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    A low-sensitivity temperature-compensated programmable BJT current-mode low-voltage filtering technique is proposed. We introduce a new technique in which the DC gain and the location of the second pole of the integrator are controlled such that the Q-enhancement, due to the second pole, is cancelled by the effect of finite DC gain. The technique is suitable for integration and can work with low-value capacitors. By making the filter time constant exactly proportional to reC, good linear tunability is achieved over many decades. The programming current is varied as proportional to absolute temperature (PTAT) to stabilize the time constant reC View full abstract»

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  • Nonlinear analysis of the Colpitts oscillator and applications to design

    Publication Year: 1999 , Page(s): 1118 - 1130
    Cited by:  Papers (74)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    This paper reports a methodological approach to the analysis and design of sinusoidal oscillators based on bifurcation analysis. The simple Colpitts oscillator is taken as an example to demonstrate this nonlinear approach for both the nearly sinusoidal and chaotic modes of operation. In particular, it is shown how regular and irregular (chaotic) oscillations can be generated, depending on the circuit parameters View full abstract»

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  • A flexible and expendable neuroimage processor architecture

    Publication Year: 1999 , Page(s): 1055 - 1063
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proof-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12×106 synapses/s.mm2 and the energy consumption is 10-9 J/synapse. A test chip was fabricated, using a 1.2-μm double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture View full abstract»

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  • Explicit formulas for the solutions of piecewise linear networks

    Publication Year: 1999 , Page(s): 1110 - 1117
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    A methodology is presented for obtaining explicit formulas for the solution of class-P piecewise linear (PL) networks and, inherently, for the linear complementary problem (LCP). The method uses the [.] operator, which has been previously defined in the literature to extend the explicit PL model descriptions of Chua. An important consequence of the methodology is that it proves that class-P networks have explicit solutions View full abstract»

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  • A dual approach to continuous-time envelope-constrained filter design via orthonormal filters

    Publication Year: 1999 , Page(s): 1042 - 1054
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    The envelope-constrained (EC) filtering problem was initially posed in the continuous-time domain as a constrained L2 space optimization problem. However, only the discretized version has been solved, using various approaches. In this paper we consider the continuous-time EC filtering problem formulated using an orthonormal basis defined on a Hilbert vector space. Caratheodory's theorem and the dual parametrization method are used to obtain a dual finite-dimensional optimization problem. Two iterative algorithms based on the gradient flow technique are then developed for solving this dual problem. The design of an EC optimal equalization filter for a communication channel is solved to illustrate the effectiveness of the proposed algorithm View full abstract»

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  • A system theory approach for designing cryptosystems based on hyperchaos

    Publication Year: 1999 , Page(s): 1135 - 1138
    Cited by:  Papers (50)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    In this paper a general methodology for designing chaotic and hyperchaotic cryptosystems is developed. The basic idea is to make the decrypter a nonlinear observer for the state of the encrypter. Referring to this concept, some propositions are given which enable the plaintext to be retrieved if proper structural properties of the chaotic system hold. The proposed tool proves to be powerful and flexible, since a wide class of cryptosystems can be designed by exploiting different chaotic and hyperchaotic circuits. The advantages of the suggested approach are illustrated in detail. In particular, the utilization of hyperchaos-based cryptosystems, as well as the increased complexity of the transmitted signal, make a contribution to the development of communication systems with higher security View full abstract»

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  • An observer-based approach for chaotic synchronization with applications to secure communications

    Publication Year: 1999 , Page(s): 1144 - 1150
    Cited by:  Papers (116)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    In this paper a systematic approach, based on the linear-state-observer design for constructing two chaotically synchronized systems, is developed. The proposed method is then applied to suggest a means to secure communications. The method combines chaotic masking and chaotic modulation, where the information signal is injected into the transmitter and simultaneously transmitted to the receiver. Furthermore, two well-known chaotic systems, Rossler and Lorenz, and a hyperchaotic Rossler system are considered as illustrative examples to demonstrate the effectiveness of the proposed approach View full abstract»

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  • Deriving technique of equivalent forms from general filter circuits and its application

    Publication Year: 1999 , Page(s): 1037 - 1041
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    In the active circuit design it is necessary to consider the designed filter features of the number of elements, element value spread, element sensitivities, and the circuit structure. For example, the desirable circuit structure of the operational transconductance amplifier-C (OTA-C) filter is that all the elements are of equal or near equal value and all the capacitors are grounded. Thus, it is important for the filter design to find the useful method to derive such a desirable equivalent structure. This paper describes the necessary and sufficient condition and a practical procedure to derive an equivalent form from a general active RC circuit or a general LCR circuit. The design examples deriving equivalent voltage controlled current source (VCCS)-C or VCCS-RC circuits from the third-order low-pass LC filter are demonstrated. By this technique it is possible to derive the suitable equivalent circuit for the implementation View full abstract»

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  • Analysis and optimization of a uniform long wire and driver

    Publication Year: 1999 , Page(s): 1086 - 1100
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    An analytical delay model of a uniform wire and driver, based on a combination of a switch-level model and Elmore delay is developed for the on-chip interconnections. The model is utilized for the optimization of delay, power, area, or combinations thereof, subject to different constraints. A linear relation between wire width and transistor widths is proposed, which leads to closed-form solutions to the optimization problems. These solutions are valid also for a multistage uniform wire and driver and are easily used in practical design. The solutions are compared to SPICE simulated results, using practical process parameters. Results show that the root of mean square (rms) errors of delay and power between SPICE simulation and the proposed method are around 3% View full abstract»

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  • A discrete approach to the control and synchronization of a class of chaotic oscillators

    Publication Year: 1999 , Page(s): 1139 - 1144
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    This work deals with the control and synchronization of chaotic systems. In the first part of the work, a general discrete-time strategy is developed to control a class of second-order uncertain nonlinear systems. The proposed strategy is based on an iterative procedure, borrowed from contraction map methodologies, and provides estimates of unmeasured states and modeling errors. Nonidentical chaotic systems can be synchronized by means of the proposed strategy. By assuming that the exact model of the oscillators is not known and that position is the only state available for measurements, the robust synchronization scheme comprises a recursive feedback-control law. Computer simulations are provided to illustrate the operation of the designed synchronization scheme View full abstract»

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  • On robust chaos suppression in a class of nondriven oscillators: application to the Chua's circuit

    Publication Year: 1999 , Page(s): 1150 - 1152
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    This paper deals with a feedback control strategy for chaos suppression. The proposed strategy is an input-output control scheme which comprises an uncertainty estimator and an asymptotic linearizing feedback. The developed control scheme allows chaos suppression in spite of modeling errors and parametric variations View full abstract»

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  • Synchronization via multiplex pulse trains

    Publication Year: 1999 , Page(s): 1072 - 1085
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    The master-slave synchronization of a complex chaotic system using multiplex pulse trains is considered. Each master outputs a chaotic pulse train of narrow pulses, the intervals of which are governed by a chaotic map. The slave system has the winner-take-all function. A simple realization of the systems is shown. We provide a theorem which guarantees the synchronization in the case that all masters and passive slaves have identical parameter values. Experiments confirm that the synchronized state changes intermittently and we clarify this mechanism. Furthermore, in order to obtain robust synchronization, a stabilization technique of the chaotic system is proposed and applied. The stabilization is guaranteed theoretically and some experimental results are given View full abstract»

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  • AER image filtering architecture for vision-processing systems

    Publication Year: 1999 , Page(s): 1064 - 1071
    Cited by:  Papers (42)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an address-event-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F(x,y) as long as it is decomposable into x-axis and y-axis components, i.e., F(x,y)=H(x)V(y), for some rotated coordinate system {x,y} and if this product can be approximated safely by a signed minimum operation. The proposed architecture is intended to be used in a complete vision system, known as the boundary contour system and feature contour system (BCS-FCS) vision model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and some electrical simulations View full abstract»

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