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Circuits, Devices and Systems, IEE Proceedings -

Issue 3 • Date Aug 1999

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Displaying Results 1 - 10 of 10
  • Compact analogue neural network: a new paradigm for neural based combinatorial optimisation

    Page(s): 111 - 116
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    The authors present a new approach to neural based optimisation, to be termed the compact analogue neural network (CANN), which requires substantially fewer neurons and interconnection weights as compared to the Hopfield net. They demonstrate that the graph colouring problem can be solved by using the CANN, with only O(N) neurons and O(N2) interconnections, where N is the number of nodes. In contrast, a Hopfield net would require N2 neurons and O(N4) interconnection weights. A novel scheme for realising the CANN in hardware form is discussed, in which each neuron consists of a modified phase locked loop (PLL), whose output frequency represents the colour of the relevant node in a graph. Interactions between coupled neurons cause the PLLs to equilibrate to frequencies corresponding to a valid colouring. Computer simulations and experimental results using hardware bear out the efficacy of the approach View full abstract»

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  • Semi-numerical static model for nonplanar-drift lateral DMOS transistor

    Page(s): 139 - 147
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    A semi-numerical static model for a nonplanar-drift lateral double-diffused MOS transistor (ND-LDMOST) is described. The modelling methodology is based on a regional approach, and its implicit equations are solved numerically. With the support of MEDICI simulations, a simplified quasi-two-dimensional analysis is used to characterise the nonplanar-drift region. The complete model is composite and accounts for LDMOST characteristics such as the doping-graded channel, the nonplanar-drift structure, and the space-charge-limited current flow in the drift region. The model equations are continuous on all operating bias conditions, which is especially important for convergence in the circuit simulator. The model predictions are in satisfactory agreement with experimental measurements. This ND-LDMOST model is suitable for incorporation into a SPICE-like circuit simulator View full abstract»

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  • Minimal-connectivity circuit for analogue sorting

    Page(s): 108 - 110
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    A CMOS circuit for sorting analogue current-mode quantities is presented. The highly modular architecture integrates several elementary cells operating at the local level. The VLSI-oriented approach minimises wiring and silicon area, because very few devices are involved. The sorting process is completed in O(n) time. Simulations at the VLSI layout level prove the effectiveness of the approach in neural-network training applications View full abstract»

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  • Innovative demodulation method for SSB technique

    Page(s): 148 - 152
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    A single sideband (SSB) demodulation method is described, in which frequency mixing is not required. The proposed method is based on the phase shift method, but no local oscillator is employed. The IQ demodulator is replaced with an envelope detector and an FM demodulator. It can replace the synchronous demodulation method, which requires an expensive phase-locked loop for carrier recovery. Not only is less interference encountered in the proposed circuit, but the production costs of the SSB and independent sideband receiver are low. Furthermore, the Doppler effect is not a serious problem since the carrier transmitted by the transmitter is used for demodulation View full abstract»

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  • PSPICE model for resistive gas and odour sensors

    Page(s): 101 - 104
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    A generalised PSPICE model of resistive gas/odour sensors is presented. The model simulates the response of both polymeric and metal oxide devices, as well as an integrated resistive heater that is used to set the operating temperature. In both cases there was good agreement between the observed responses and the PSPICE simulated responses to rectangular pulses of gases. The PSPICE model is not only simpler and faster to use than analytical solutions, but also should permit the rapid prototyping of associated drive circuitry View full abstract»

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  • Low-power circuit implementation for partial-product addition using pass-transistor logic

    Page(s): 124 - 129
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    A low-power circuit implementation that performs partial-product addition within a 16×16-bit parallel multiplier is presented. The circuits are based on 0.8 μm and 0.35 μm BiCMOS processes and utilise mainly pass-transistor logic circuits. Unlike other pass-transistor implementations reported, the proposed circuits fully exploit the non-full-swing nature of the pass-transistor circuits, thus achieving low power operation. Despite the poorer current drive capability of the non-full-swing nodes, speed performance is maintained by stacking as few pass transistors in series as possible, and keeping the capacitive loading of the non-full-swing nodes as low as possible. The proposed implementation consists of a low-power 32-bit carry-select (CS) two-operand adder and a Wallace tree adder utilising a non-full-swing pass-transistor 4-2 compressor. Significant improvement in terms of power has been achieved when compared with existing circuits, thus making the proposed implementation suitable for a low-power high performance multipliers View full abstract»

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  • Analogue divider using integral compare mode and its application

    Page(s): 105 - 107
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    An analogue divider of integral compare mode which basically consists of two integral operators, a comparator and three electronic switches is described. The circuit has been applied to test the voltage ratio of varistors. Experiments shows that it can meet the demand for precision in practical applications by circuit design and the deliberate choice of the devices and elements concerned View full abstract»

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  • GaAs MESFET with low current capability grafted onto quartz substrate

    Page(s): 135 - 138
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    DC characteristics of a GaAs MESFET, which is grafted onto an optically flat quartz substrate, are presented and discussed. The authors utilised a GaAs MESFET having small current capability in order to avoid heat effects and to magnify the effects brought by transplantation. Improved pinch-off and saturation behaviours, as well as increased drain-gate breakdown voltage, stemming from the insulating property of the quartz substrate were observed. Negative shift of threshold voltage and degraded low-field mobility were also observed and both were attributed to the stresses acting on the active region View full abstract»

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  • Novel 1-V full-swing high-speed BiCMOS circuit using positive feedback base-boost technique

    Page(s): 130 - 134
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A novel 1-V full-swing BiCMOS logic circuit, using a positive feedback base-boost technique for high-speed applications, is described. Simulation results show that the circuit outperforms the best existing non-complementary BiCMOS circuits in terms of speed, power consumption and chip area. Based on 0.35 μm BiCMOS technology, the proposed circuit offers 49% delay reduction with negligible increase in power dissipation over the CMOS circuit at a supply voltage of 1 V and a load capacitance of 1pF. The crossover capacitance of the proposed circuit is as low as 0.1 pF, and experimental results confirm its circuit operation View full abstract»

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  • Paired Haar spectra computation through operations on disjoint cubes

    Page(s): 117 - 123
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    Paired Haar spectra for systems of incompletely specified Boolean functions are calculated from arrays of disjoint cubes. The method is based mainly on two basic cube operations of shifting and addition that can be efficiently implemented by computer. The method can calculate only a few selected coefficients or all of them in parallel. To further reduce computational requirement only nonvanishing coefficients are stored View full abstract»

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