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Design & Test of Computers, IEEE

Issue 3 • Date July-Sept. 1999

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Displaying Results 1 - 14 of 14
  • Origin of the stuck-at model [Letter to the Editor]

    Publication Year: 1999 , Page(s): 8
    Save to Project icon | Request Permissions | PDF file iconPDF (106 KB)  
    Freely Available from IEEE
  • Guest Editor's Introduction: test and product life cycle

    Publication Year: 1999 , Page(s): 20 - 22
    Save to Project icon | Request Permissions | PDF file iconPDF (426 KB)  
    Freely Available from IEEE
  • Test and reliability: partners in IC manufacturing. 1

    Publication Year: 1999 , Page(s): 64 - 71
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (507 KB)  

    This article explains the major IC reliability failure mechanisms with perspectives on their severity and relation to test. View full abstract»

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  • RF integration into CMOS and deep-submicron challenges

    Publication Year: 1999 , Page(s): 112 - 116
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (274 KB)  

    First Page of the Article
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  • Economic online self-test in the time-triggered architecture

    Publication Year: 1999 , Page(s): 81 - 89
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (112 KB)  

    Traditional online self-testing methods in event-triggered systems compromise system responsiveness or result in costly solutions. The testing strategy presented here takes advantage of the properties offered by a time-triggered system to avoid interfering with system responsiveness while maintaining low test overhead View full abstract»

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  • Boundary scan: the Internet of test

    Publication Year: 1999 , Page(s): 34 - 43
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (124 KB)  

    Boundary scan enables us to reuse tests developed at different design levels and in different life-cycle phases. By facilitating communication between previously isolated areas, built-in boundary scan becomes what the authors call the “Internet of Test” View full abstract»

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  • Automating PBX system testing

    Publication Year: 1999 , Page(s): 44 - 52
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (108 KB)  

    Manually testing telephone features such as call forwarding and advice of charge is costly. A new method based on TTCN, an ISO-standardized test specification language, automates the process and helps meet product quality and time-to-market demands View full abstract»

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  • Generating functional design verification tests

    Publication Year: 1999 , Page(s): 53 - 63
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (104 KB)  

    The Robust Test Method, a functional test generation methodology, translated into a quantum jump in test quality at Ford. Applied to subsystem-level design verification, it detected more errors than module and system test combined, while reducing test turnaround time by 30% View full abstract»

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  • Testing methodology for FireWire

    Publication Year: 1999 , Page(s): 102 - 111
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (208 KB)  

    This article describes a methodology for testing a high-performance serial bus interface commonly referred to as FireWire. Specified by the IEEE 1394 document, FireWire is offered by IC manufacturers in various scalable configurations. In general, it is a low-cost device used to provide a highspeed data path between various systems and products, such as PCs and video devices. FireWire is also usab... View full abstract»

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  • Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering

    Publication Year: 1999 , Page(s): 72 - 80
    Cited by:  Papers (88)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (196 KB)  

    Designing at higher levels of abstraction is key to managing the complexity of today's VLSI chips. The authors show how they reverse-engineered the ISCAS-85 benchmarks to add a useful, new high-level tool to the designer's arsenal View full abstract»

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  • Fault-secure parity prediction Booth multipliers

    Publication Year: 1999 , Page(s): 90 - 101
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (220 KB)  

    Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding View full abstract»

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  • System-on-chip design: impact on education and research

    Publication Year: 1999 , Page(s): 11 - 19
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (96 KB)  

    Deep-submicron technology is rapidly leading to exceedingly complex, billion-transistor chips. Within a decade, these chips will deliver enormous computing power as well as RF and analog interfaces for information and communication technology. At the same time, portability and the need for inexpensive packaging will limit power consumption to a few watts or less. These systems-on-chip (SOCs), desi... View full abstract»

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  • Design for test and time to market: a personal perspective

    Publication Year: 1999 , Page(s): 23 - 27
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (60 KB)  

    This article explores design for test implementation alternatives and electronic design for test automation's effects on overall time to market View full abstract»

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  • Board test and the product life cycle. Get wise to board test strategies

    Publication Year: 1999 , Page(s): 28 - 33
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    In the board test world many test strategies are alive and kicking. It would be nice to think that each of these has been honed over many years of study and measured performance to yield the optimal balance of cost, quality, and service required by each enterprise. The reality is that most strategies evolve in isolation to satisfy current objectives. Usually these objectives are reactions to marke... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty