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Design & Test of Computers, IEEE

Issue 3 • Date July-Sept. 1999

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Displaying Results 1 - 14 of 14
  • Origin of the stuck-at model [Letter to the Editor]

    Page(s): 8
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    Freely Available from IEEE
  • Guest Editor's Introduction: test and product life cycle

    Page(s): 20 - 22
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    Freely Available from IEEE
  • Test and reliability: partners in IC manufacturing. 1

    Page(s): 64 - 71
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    This article explains the major IC reliability failure mechanisms with perspectives on their severity and relation to test. View full abstract»

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  • RF integration into CMOS and deep-submicron challenges

    Page(s): 112 - 116
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    First Page of the Article
    View full abstract»

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  • Automating PBX system testing

    Page(s): 44 - 52
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    Manually testing telephone features such as call forwarding and advice of charge is costly. A new method based on TTCN, an ISO-standardized test specification language, automates the process and helps meet product quality and time-to-market demands View full abstract»

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  • Design for test and time to market: a personal perspective

    Page(s): 23 - 27
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    This article explores design for test implementation alternatives and electronic design for test automation's effects on overall time to market View full abstract»

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  • Generating functional design verification tests

    Page(s): 53 - 63
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    The Robust Test Method, a functional test generation methodology, translated into a quantum jump in test quality at Ford. Applied to subsystem-level design verification, it detected more errors than module and system test combined, while reducing test turnaround time by 30% View full abstract»

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  • Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering

    Page(s): 72 - 80
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    Designing at higher levels of abstraction is key to managing the complexity of today's VLSI chips. The authors show how they reverse-engineered the ISCAS-85 benchmarks to add a useful, new high-level tool to the designer's arsenal View full abstract»

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  • Economic online self-test in the time-triggered architecture

    Page(s): 81 - 89
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    Traditional online self-testing methods in event-triggered systems compromise system responsiveness or result in costly solutions. The testing strategy presented here takes advantage of the properties offered by a time-triggered system to avoid interfering with system responsiveness while maintaining low test overhead View full abstract»

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  • System-on-chip design: impact on education and research

    Page(s): 11 - 19
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    Deep-submicron technology is rapidly leading to exceedingly complex, billion-transistor chips. Within a decade, these chips will deliver enormous computing power as well as RF and analog interfaces for information and communication technology. At the same time, portability and the need for inexpensive packaging will limit power consumption to a few watts or less. These systems-on-chip (SOCs), designed at the processor-memory level, will fuel the future information society. Such designs depend, however, on SOC architects who can bridge the gap between software-centric system specifications and their implementation in novel, energy-efficient silicon architectures. Designing such hardware-software platforms will require a global-system approach from concept to implementation, which may well require a rethinking of present engineering schools. Chips will no longer be stand-alone components but complete silicon boards encapsulating complex system knowledge. These boards will be specified far above the hardware-description-language level and implemented in new, heterogeneous architectures designed at the processor-memory level. Today we know very little about the nature of these future architectures, let alone the design methodology. We will instead need the design research center concept. The research center's goal will be to perform cross-disciplinary system design research to create new methodologies, tools, libraries, and courses-distributed via the Internet-to produce enough SOC architects worldwide View full abstract»

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  • Fault-secure parity prediction Booth multipliers

    Page(s): 90 - 101
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    Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding View full abstract»

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  • Boundary scan: the Internet of test

    Page(s): 34 - 43
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    Boundary scan enables us to reuse tests developed at different design levels and in different life-cycle phases. By facilitating communication between previously isolated areas, built-in boundary scan becomes what the authors call the “Internet of Test” View full abstract»

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  • Board test and the product life cycle. Get wise to board test strategies

    Page(s): 28 - 33
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    In the board test world many test strategies are alive and kicking. It would be nice to think that each of these has been honed over many years of study and measured performance to yield the optimal balance of cost, quality, and service required by each enterprise. The reality is that most strategies evolve in isolation to satisfy current objectives. Usually these objectives are reactions to market demands that filter (or more normally, fly down to the test engineering department. When we look across the many markets for electronic assemblies, we see a wide range of test strategies. We can broadly group the market-driven strategies into the product's end use. For example, military equipment test strategies differ from consumer products, for some obvious operational requirements but also for some other factors. The same differences in strategy are seen between other market groups such as telecommunications and PC products. We can speculate on the technical justification for these differences. However, someone from outside our industry would quickly suspect that a product test strategy is related more to the selling price the market attracts than its technical content. It could be argued that the highest technology products attract the highest price because they also require extensive testing. But is this wholly true? Why does a PC motherboard production test process differ from a telecommunications switching card? Both use similar component packaging styles and assembly technologies and have sold millions globally. Of course, this is an over simplification of a complex set of problems, especially when we consider the requirement to comply with a whole range of regulations, but it raises issues we should not ignore View full abstract»

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  • Testing methodology for FireWire

    Page(s): 102 - 111
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    This article describes a methodology for testing a high-performance serial bus interface commonly referred to as FireWire. Specified by the IEEE 1394 document, FireWire is offered by IC manufacturers in various scalable configurations. In general, it is a low-cost device used to provide a highspeed data path between various systems and products, such as PCs and video devices. FireWire is also usable as a backplane bus interconnect. Application-specific IC manufacturers offer FireWire standard cells for use in custom device designs. To assure cost-effective production, the tester and implementation costs must be reasonable, the execution time must be short, and test results must be accurate. Our methodology fulfils these goals with a minimum of compromises. We validated it using a plastic leaded chip carrier device with an 8-bit parallel port and multiple serial ports on an Advantest T6682 VLSI Logic Test System View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty