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Advanced Packaging, IEEE Transactions on

Issue 3 • Date Aug. 1999

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Displaying Results 1 - 25 of 38
  • Correction to "Frequency response characteristics of reference plane effective inductance and resistance"

    Publication Year: 1999 , Page(s): 524
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  • Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects

    Publication Year: 1999 , Page(s): 309 - 320
    Cited by:  Papers (11)
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    Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long lines become highly resistive and have unacceptable delays. One possible solution to the problem of long lossy lines is to transfer these lines off-chip using seamless high off-chip connectivity (SHOCC) technology. In this work, me modeled and studied the electrical performance of SHOCC signal lines. The performance of SHOCC interconnects was compared with that of typical on-chip interconnerts. Modeling and simulation results, along with recommendations with regards to driver sizes and the type of interconnect that should be used, are presented View full abstract»

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  • RF/microwave characterization of multilayer ceramic-based MCM technology

    Publication Year: 1999 , Page(s): 326 - 331
    Cited by:  Papers (23)  |  Patents (4)
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    We present RF/microwave characterization of a 20-layer ceramic-based multichip module (MCM-C) on low temperature co-fired ceramic (LTCC). We investigated material properties and performance of embedded passives by design, fabrication and characterization of planar and multilayer integral inductors. Uniform dielectric constant, low loss property and high Q passives fabricated using this technology demonstrate the feasibility for implementing hybrid RF/microwave systems View full abstract»

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  • Electrical characterization of ball grid array packages from S-parameter measurements below 500 MHz

    Publication Year: 1999 , Page(s): 343 - 347
    Cited by:  Papers (3)
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    Ball grid array (BGA) packages have been characterized from one port S-parameter measurements by shorting and opening the connection on the ball side of BGA packages. Transmission line parameters (resistance, inductance and capacitance) using the Γ equivalent circuit model are extracted from the measured S11 parameter. Extracted resistances are strongly dependent on frequency, but extracted inductances and capacitances are nearly constant up to 500 MHz. Extracted capacitances are well matched to those measured from an LCR meter and calculated from a three-dimensional (3-D) simulator, Capacitance in a transmission line plays an important role in electrical performance for packages so that we may model a transmission line as a single capacitor. Extracted capacitances using the single capacitor model also well represent the measured S11. These results suggest that the single capacitor model can be efficiently used for the transmission line model in BGA packages up to 500 MHz View full abstract»

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  • A compact MU-interface, 2.5-Gb/s optical transmitter module with LD-driver IC embedded in L-shaped wiring substrate

    Publication Year: 1999 , Page(s): 451 - 459
    Cited by:  Papers (3)
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    A 6.2-cc MU interface optical transmitter module has been developed in a compact packaging configuration that allows modules to be mounted side by side on a system board. The module employs an MU receptacle for optical output and miniature coaxial receptacles for electrical input. An L-shaped high-speed wiring substrate in a package cavity allows thermal isolation of a laser-diode driver IC (LD-DR) from the 1.55-μm distributed feedback laser diode (DFB-LD) mounted on a thermoelectric (TE) cooler. A confocal two-aspheric-lens circuit is used for high-performance coupling of the DFB-LD to a dispersion-shifted fiber (DSF). A module using the proposed configuration has been evaluated at temperatures from 10-65°C. Experiments with the module showed good electrical performance at a bit rate of 2.5 Gb/s, low power dissipation (less than 1.8 W; only 0.33 W for the LD-DR), and high optical coupling efficiency (over 50%) View full abstract»

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  • Thermosonic flip-chip bonding system with a self-planarization feature using polymer

    Publication Year: 1999 , Page(s): 468 - 475
    Cited by:  Papers (13)
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    Thermosonic flip-chip bonding is a wire bonding technology modified for flip-chip assembly. Compared with the soldering technology, it is simpler, faster and more cost-effective. Unfortunately, the yield of thermosonic bonding is low and unreliable because it is difficult to control the ultrasonic energy transmission. A small planarity angle between the bonding tool and stage can result in a nonuniform ultrasonic energy distribution. A self-planarization concept was proposed to solve this problem. A layer of polymer was placed between the bonding tool and the chip to smooth the nonplanar contact. Experimental measurements and finite element modeling were used to study the effect of the polymer layer. Results showed that the polymer layer could assure a uniform ultrasonic energy distribution; however, it also reduced the energy transmission efficiency. A case study for optimization was conducted based on finite element modeling. For a 1000-I/O flip chip assembly with a 250 μm pitch using a bonder with a 0.01° planarity angle, polymer thickness of 350 μm and a Young's modulus of 2 GPa were selected View full abstract»

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  • S-parameter based technique for simultaneous switching noise analysis in electronic packages

    Publication Year: 1999 , Page(s): 267 - 273
    Cited by:  Papers (1)
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    A method based on S-parameters is developed for the analysis of simultaneous switching noise (SSN) in electronic packages. A two-port Z matrix of the package pin/trace, and the coupling between the pins/traces are modeled by analytical equations. SSN is analyzed as a function of the number of switching drivers and switching time. Frequency domain measurements are performed to demonstrate the accuracy of the model. The modeling methodology is applied to both leaded and area array packages View full abstract»

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  • International conference on multichip modules and high density packaging

    Publication Year: 1999 , Page(s): 365
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  • Reducing simultaneous switching noise and EMI on ground/power planes by dissipative edge termination

    Publication Year: 1999 , Page(s): 274 - 283
    Cited by:  Papers (57)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    Power and ground planes are required to have low impedance over a wide range of frequencies. Parallel ground and power planes in multilayer printed-circuit boards exhibit multiple resonances, which increase the impedance and also the radiation from the edge of the board. Resistive termination along the board edges reduces the resonance peaks. Simple and straightforward design expressions, simulated self and transfer impedances, as well as measured impedance plots are presented for power-ground planes View full abstract»

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  • Contribution of resonance to ground bounce in lossy thin film planes

    Publication Year: 1999 , Page(s): 249 - 258
    Cited by:  Papers (5)
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    This paper discusses the pulse propagation effects on lossy thin film planes. The ground bounce phenomena produced by the resonance on planes has been captured using a combination of modeling techniques and measurements. Macromodeling method has been used to explain the transient phenomena on planes by using the dominant poles and residues of the system View full abstract»

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  • Special section from the 48th electronic components and technology conference

    Publication Year: 1999 , Page(s): 384
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  • Epoxy-based aqueous-processable photodielectric dry film and conductive ViaPlug for PCB build-up and IC packaging

    Publication Year: 1999 , Page(s): 385 - 390
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    DuPont formulated a new generation of photoimageable permanent resists and conductive ViaPlug polymer to be used as building blocks for sequential build-up of printed circuit boards (PCB's), multichip module-laminates (MCM-Ls), and plastic integrated circuit (IC) packages. The buzzwords for these structures are high density interconnection structures (HDIS) and microvias. The conventional method of making PCB's and MCM-Ls is a sequential lamination of innerlayer cores or interplanes, followed by at least one mechanical drilling. In this paper we will discuss a new approach of using semi-additive plating which means starting with a multilayer core, mechanically drilling for through hole connection, filling the through-hole with conductive ViaPlug, then adding layers of dielectric to make blind or buried vias for interconnection and routing of circuits, and heat dissipation. The paper will discuss the challenges in each application, relevant industry specifications for each application, and the dielectric and conductor materials properties to meet the challenges. From the viewpoint of technology choices, we will compare photoimaging versus laser ablation and plasma etching. Lastly, we will discuss our reliability data developed internally and in conjunction with several consortia View full abstract»

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  • Transient two-dimensional thermal analysis of electronic packages by the boundary element method

    Publication Year: 1999 , Page(s): 476 - 486
    Cited by:  Papers (4)
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    The fabrication of electronic packages involves heating and then cooling from high processing temperatures. Because these devices consist of bonded materials with different thermal and mechanical properties, high thermomechanical stresses develop due to thermal and stiffness mismatches of bonded materials at regions with geometric and/or material discontinuities. These high stresses may result in crack initiations, leading to delaminations. Therefore, accurate temperature and flux distributions are critical when computing thermomechanical stresses, knowledge of which is essential for reliable designs. This study presents an analysis method based on the boundary element method (BEM) to investigate the transient thermal response of electronic packages consisting of dissimilar materials while subjected to general boundary conditions. In order to demonstrate its capability, a chip on a substrate configuration subject to convective cooling is considered. The boundary conditions across the interfaces between the chip and the adhesive and adhesive and substrate are matched through exact expressions. The results capture the singular flux field arising from the mismatch in the thermal conduction coefficients and geometric discontinuity. The comparison of the results with those obtained from finite element analysis shows that BEM is rather robust and efficient for this class of transient conduction analyses View full abstract»

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  • Frequency-dependent crosstalk simulation for on-chip interconnections

    Publication Year: 1999 , Page(s): 292 - 308
    Cited by:  Papers (22)  |  Patents (3)
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    An extensive study of crosstalk simulation issues for on-chip interconnections was performed for representative six-layer Al(Cu) structures. Guidelines are given for the range of conditions when R(f)L(f)C versus RLC versus RC circuit representations are valid. Examples are also given of realistic short and long coupled-section interactions and the effect of in-plane neighboring connections is discussed. A frequency-dependent crosstalk simulation technique is shown. All simulation results are verified through measurement of a comprehensive set of experiments built with a large range of line widths and spaces on various layers with both in-plane and vertical coupling. Signal propagation and crosstalk are analyzed over the temperature range -160°C to +100°C and interconnect bandwidth limitations predictions are given View full abstract»

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  • Stress-buffer and passivation processes for Si and GaAs IC's and passive components using photosensitive BCB: process technology and reliability data

    Publication Year: 1999 , Page(s): 487 - 498
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB)  

    Polymer coatings are applied to chips and passive components to provide stress relief between the device/component and the plastic package and/or to provide mechanical and environmental protection. The semiconductor industry is actively pursuing a one mask, photosensitive dielectric process for stress-buffer and secondary passivation of memory die. A one mask photo-benzocyclobutene (BCB) process is compared to traditional two mask wet etch processes. This new one mask process reveals 1/3 the total wafer processing time and equivalent reliability (traditional MIL 883C testing) for passivated 100 lead static random access memory components (SRAMs). Reliability data are also presented for GaAs chips, and NiCr and TaN resistors which have been passivated by BCB View full abstract»

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  • Mechatronics for automotive and industrial applications

    Publication Year: 1999 , Page(s): 433 - 441
    Cited by:  Papers (2)
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    Mechatronics is a multidisciplinary field, which offers low cost system solutions based on the principle of homogenizing system components and consequently to eliminate at least one material component or packaging level from the system. This leads to a decrease in the number of interconnects between the mechanical parts and the next digital bus. This system approach shows, compared to the existing solutions, a higher functionality, more intelligence, and better reliability performance. The number of interconnects necessary to link a motor, or sensor, or an actuator, to the next digital bus decreases, as the smartness of the devices increases View full abstract»

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  • Thermal management for multifunctional structures

    Publication Year: 1999 , Page(s): 379 - 383
    Cited by:  Papers (9)
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    Multifunctional structures (MFS) are an innovative concept that offer a new methodology for spacecraft design, eliminating chassis, cables and connectors, and integrating the electronics into the walls of the spacecraft. The MFS design consists of multilayer flexible circuit patches bonded onto a structural composite panel, and multichip modules (MCMs) performing specific functions are bonded onto the circuit patches which are interconnected via flexible circuit jumpers. Incorporation of the high power density two-dimensional (2-D) and three-dimensional (3-D) MCM's into smaller and more efficient packaging designs still has the fundamental requirement to maintain component temperatures within design limits. Higher component qualification temperatures, such as 393 K, can result in smaller spacecraft radiator areas that are consistent with efficient packaging schemes. During the MFS development effort, a structural radiator panel was fabricated using high thermal conductivity (Hi-K) composite facesheets, and several thermal management designs using combinations of Hi-K doublers (150-1500 W/m-K), Hi-K (150-700 W/m-K) corefill, and deployable radiators to maximize MCM's heat rejection. Results of the thermal vacuum tests and details of the thermal design methodology are presented in this paper View full abstract»

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  • A new discrete transmission line model for passive model order reduction and macromodeling of high-speed interconnections

    Publication Year: 1999 , Page(s): 356 - 364
    Cited by:  Papers (29)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    A new, computationally efficient, discrete model is presented for passive model order reduction of high-speed interconnections. The proposed discrete model is based on the use of the theory of compact finite differences for the development of the discrete approximation to the transmission line equations that govern wave propagation on the interconnections. Thus result in a discrete model that utilizes only a few unknowns per wavelength and yet provides highly accurate waveform resolution. In addition to improved computational efficiency, the generated discrete model is passive, and compatible with the passive reduced-order interconnect modeling algorithm (PRIMA). Thus, it is suitable for the development of passive reduced-order models of interconnection networks of high complexity. Numerical experiments from the simulation and model order reduction of coupled interconnections are used to illustrate the validity and efficiency of the proposed model View full abstract»

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  • A 3-D stacked chip packaging solution for miniaturized massively parallel processing

    Publication Year: 1999 , Page(s): 424 - 432
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1448 KB)  

    The development and evaluation of a three-dimensional (3-D) interconnect and packaging technology for massively parallel processor (MPP) implementation is reported. Following reviews of specific modular massively parallel computer (MPC) accelerator and chip stacking technologies, the paper reports the progress of a collaborative research project to pioneer a novel MPP module. The design of a highly compact 3-D chip-stack, integrating five MPP chips in a single package, is described in detail. Problems encountered and their solutions are reported. Test results for prototype MPP chip-stacks provide proof-of-principle for the 3-D chip stacking approach. Allowing from 2:1 to 4:1 savings in the modular MPC implementation size, without significant increase in cost or loss of performance, the emerging MPP chip stacking technology offers a cost-effective solution for MPP miniaturization View full abstract»

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  • Efficient computation of interconnect capacitances using the domain decomposition approach

    Publication Year: 1999 , Page(s): 348 - 355
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    In this paper, we present a novel technique for efficient computation of capacitance matrices of complex interconnect configurations. It applies the finite difference (FD) method in conjunction with the perfectly matched layer (PML) and impedance boundary condition for mesh truncation, and combines these with the overlapping domain decomposition approach to handle complex configurations that are too large to handle in one step. Convergence and efficiency issues of the proposed algorithm are examined and numerical examples are presented to illustrate the usefulness of the proposed scheme View full abstract»

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  • Contributions from the seventh topical meeting on electrical performance of electronic packaging

    Publication Year: 1999 , Page(s): 238 - 239
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  • Design and characteristics of a newly developed cavity-up plastic and ceramic laminated thin BGA package

    Publication Year: 1999 , Page(s): 460 - 467
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    The key requirements for a package are high electric and thermal performance, thinness, light weight, small size or high assembly density, and low cost. Plastic packages are superior in terms of electrical performance and cost whereas highly thermally conductive ceramic packages are superior in terms of thermal performance, weight, and size. However, these conventional plastic or ceramic packages cannot simultaneously satisfy all the requirements A new cavity-up plastic and ceramic laminated package (PCLP) has been developed that not only has superior electrical and thermal characteristics simultaneously without a heat sink, but also a thin profile and small size and is cost-effective. For example, the frequency range applicable to the PCLP exceeds 500 MHz, the maximum power dissipation is 4 W under natural convection, and the thickness is less than 2 mm. The PCLP is composed of two substrates: an electrically conductive plastic substrate and thermally conductive ceramic substrate. The plastic substrate, made of liquid crystal polymer (LCP) and copper, forms a flexible printed circuit (FPC). LCP is a suitable material since it has low water absorption, low dielectric constant, and low dielectric loss. The ceramic substrate is cofired tungsten-metallized aluminum nitride (AlN). It has high thermal conductivity and its coefficient of thermal expansion (CTE) is close to that of silicon. The AlN substrate also supports mechanically both the FPC and the semiconductor chip. The package is made using simple processes: both FPC and AIN substrate are single insulation layers; interconnection technologies are simple, for example, screened bump interconnection and lamination; and a conventional pattern formation is used, for example, screen printing. The measured electrical resistance is 450 mΩ (line length 14.7 mm, width=50 μm), which was about 1/10 of that for a simple ceramic cofired package of the same dimensions with a tungsten conductor. The measured thermal resistance is 10.8°C/W under natural convection without a heat sink. In this paper the PCLP's design concept, configuration and performance characteristics are reported View full abstract»

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  • Modeling of power distribution systems for high-performance microprocessors

    Publication Year: 1999 , Page(s): 240 - 248
    Cited by:  Papers (20)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    This paper presents approximate techniques for building models and simulating the response of power distribution systems for high-performance microprocessors. Several distributed equivalent SPICE circuit models were built by extracting the appropriate resistance, inductance, capacitance (RLC) component values using a combination of two-dimensional (2-D) and three-dimensional (3-D) quasi-static field solvers. They were used to assess how well such effects as system transfer impedance and transient characteristics can be predicted. The models include the chip, its controlled collapsed chip connection (C4) connections to the package, the power distribution structure in the package, connector and motherboard. It is found that the response of the entire power system can be treated as a second order system, by which the main features of the performance of the power delivery network are assessed. Samples of transient and frequency domain data for typical microprocessors are given and the effects of some design options are discussed, as are the tradeoffs in model complexity versus the gain of useful design information View full abstract»

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  • Electrical evaluation of flip-chip package alternatives for next generation microprocessors

    Publication Year: 1999 , Page(s): 407 - 415
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (988 KB)  

    Two styles of flip-chip packages for next-generation microprocessors were designed: a low-cost organic ball-grid-array (BGA) and a thin-film-on-ceramic land-grid array (LGA). Simultaneous switching output (SSO) noise, and core noise were measured. Although SSO was improved by a factor of two over the previous generation of packaging, core noise was still quite significant. We found that core noise is best managed by placing low-inductance capacitance close to the noise source, i.e., using on-chip capacitors, coupled planes in the package, or on-package bypass capacitors. Because of the lower impedance of its power planes, the ceramic package showed significantly better electrical performance than the organic. Addition of on-package bypass capacitors greatly narrows the gap between the two packages View full abstract»

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  • Ten-channel optical transmitter module for sub-system interconnection operating at λ=1.3 μm up to 12.5 Gbit/s

    Publication Year: 1999 , Page(s): 442 - 450
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    Parallel optical interconnection devices feature wide bandwidth, low loss and cross-talk, small size and weight along with low power consumption and cost. They appear particularly suitable to replace the electrical interconnections wherever high connection density and transmission capacity are required (e.g., in board-, cabinet-, and building interconnections). We report on a 10-channel parallel optical transmitter module with a 12.5 Gbit/s total bit-rate. The module includes a commercial 10-channel Fabry-Perot laser array chip) emitting at λ=1.3 μm, coupled to a standard 50/125 μm multimode fiber ribbon, and a silicon CMOS laser driver IC. The IC allows low power consumption even at the high bit-rate achieved, and therefore requires only a passive thermal management, contributing to lower the costs. The output optical power of both logicall 0 and 1 levels can be adjusted externally. The module operates up to 1.25 Gbit/s/ch, exhibiting at a bit error ratio (BER) better than 10-14. With a power budget of more than 10 dB and a power consumption of 130 mW per channel. An interconnection distance in excess of 1200 m has been demonstrated, with a residual power margin of 4 dB without BER degradation. In this way our transmitter gives interconnection distances in excess of 500 m, not attainable with the shorter wavelengths given by surface emitters, and permits low power dissipation (low threshold light source and CMOS circuits) and low cost fabrication. Such characteristics make the module interesting for applications in which medium-long distances are involved and high bit-rates required, but reduced power consumption and dimensions are mandatory, as for interconnections between submodules in the large switching nodes of new generation View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering