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IEE Proceedings - Computers and Digital Techniques

Issue 2 • Date Mar 1999

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Displaying Results 1 - 9 of 9
  • Cryptanalysis and improvement of Petersen-Michels signcryption scheme

    Publication Year: 1999, Page(s):123 - 124
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (284 KB)

    Petersen and Michels showed that Zheng's signcryption schemes lose confidentiality to gain nonrepudiation. They also proposed another signcryption scheme modified from a signature scheme giving message recovery. The authors show that the Petersen-Michels scheme still violates the unforgeability property, and propose an improvement that overcomes the security leak inherent in the scheme. The improv... View full abstract»

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  • Test and diagnosis of faulty logic blocks in FPGAs

    Publication Year: 1999, Page(s):100 - 106
    Cited by:  Papers (17)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (644 KB)

    Field programmable gate arrays (FPGAs) have been used in many areas of digital design. Because FPGAs are programmable, faults in them can be easily tolerated once fault sites are located. However, diagnosis of faults in FPGA has not yet been explored by researchers. A new methodology for the testing and diagnosis of faults in FPGAs is presented, based on built-in self-test. The proposed method imp... View full abstract»

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  • Power-driven technology mapping using pattern-oriented power modelling

    Publication Year: 1999, Page(s):83 - 89
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (616 KB)

    Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several pieces of research. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch. The authors propose a pattern-oriented power modelling for improved technology mapping. We first perform a profi... View full abstract»

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  • Security of Shao's signature schemes based on factoring and discrete logarithms

    Publication Year: 1999, Page(s):119 - 121
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (364 KB)

    In 1998, Shao proposed two new digital signature schemes which were claimed to be unbreakable if the factorisation and the discrete logarithms are simultaneously unsolvable. However, this paper shows that, if the factorisation problem can be solved, Shao's signature schemes can be broken View full abstract»

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  • Computers and Digital Techniques

    Publication Year: 1999, Page(s):0_1 - 0_2
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (168 KB)

    First Page of the Article
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  • Parallel implementation of simulated annealing using transaction processing

    Publication Year: 1999, Page(s):107 - 113
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (528 KB)

    Simulated annealing is an effective method for solving large combinatorial optimisation problems. Because of its iterative nature the annealing process requires a substantial amount of computation time. A new parallel implementation based on the concurrency control theory of database systems is presented; the parallelised annealing process is serialisable. Concurrent updates to the base solution a... View full abstract»

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  • High throughput and low-latency implementation of bit-level systolic architecture for 1D and 2D digital filters

    Publication Year: 1999, Page(s):91 - 99
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (560 KB)

    Systolic architectures are presented for bit-level VLSI implementation of 1D and 2D digital filters. The hardware utilisation in both our structures is 100%, and the throughput rate is 1 bit per clock period where the duration of a clock period is one full addition time. The structures have a very low latency of only three-cycle periods for the 1D FIR, four-cycle periods for 1D IIR and 2D FIR and ... View full abstract»

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  • Highly fault-tolerant hypercube multicomputer

    Publication Year: 1999, Page(s):77 - 82
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (564 KB)

    A strongly fault-tolerant design for a d-dimentrun “aucountsional hypercube multiprocessor is presented and its reconfigurability examined. The augmented hypercube has a spare node connected to each node of a subcube of dimension i, and the spare nodes are also connected as a (d-i)-dimensional hypercube. By utilising the circuit-switched capabilities of the communication modules of the spare... View full abstract»

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  • Hardware implementation of RAM-based neural networks for tomographic data processing

    Publication Year: 1999, Page(s):114 - 118
    Cited by:  Papers (1)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (444 KB)

    The hardware discussed in the paper employs field programmable logic devices to interface with memory components and unlike previous implementations, utilises dynamic RAM without compromising performance. The network offers the opportunity to estimate process parameters without recourse to image reconstruction. Tests reveal speedups of 17, 22 and 6 for image reconstruction, void fraction estimatio... View full abstract»

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