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Electron Device Letters, IEEE

Issue 8 • Date Aug. 1999

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Displaying Results 1 - 17 of 17
  • A new self-aligned offset staggered polysilicon thin-film transistor

    Publication Year: 1999 , Page(s): 381 - 383
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    A new self-aligned offset staggered polysilicon thin-film transistor (poly-Si TFT) has been proposed and demonstrated to have a suppressed leakage current. For the self-aligned offset structure, planarization with thick photoresist and etchback of photoresist are successfully utilized. The offset length can be easily controlled by the thickness of the gate material without photolithographic limitation. In the self-aligned offset polysilicon TFT's, the leakage current decreases with an increasing offset length. View full abstract»

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  • Roles of sidewall oxidation in the devices with shallow trench isolation

    Publication Year: 1999 , Page(s): 384 - 386
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    The effects of sidewall sacrificial and sidewall oxidations on the characteristics of devices with shallow trench isolation (STI) have been investigated. We found that sidewall sacrificial and sidewall oxidations significantly affected junction leakage and gate oxide integrity (GOI). The sidewall sacrificial oxidation was shown to reduce oxidation-induced stresses and make the trench top corner more rounded. This reduced stress and more rounded top corner led to much improved junction leakage and GOI. These results clearly show that the sidewall sacrificial oxidation is worth using, although it adds complexity to the STI process. View full abstract»

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  • A comparison of hydrogen and deuterium plasma treatment effects on polysilicon TFT performance and dc reliability

    Publication Year: 1999 , Page(s): 387 - 389
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (54 KB)  

    We compare the performance and dc reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFT's) after passivation by plasma deuteration and conventional plasma hydrogenation. An optimum deuteration temperature of 300/spl deg/C is found, as compared to 350/spl deg/C for hydrogenation. Deuteration yields comparable TFT performance as hydrogenation, while deuterated TFT's exhibit increased resistance to threshold voltage degradation under dc stress. These results indicate that deuteration is a promising alternative to hydrogenation for achieving high-performance, high-reliability poly-Si TFT's for applications such as flat-panel displays. View full abstract»

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  • Field and temperature dependence of TDDB of ultrathin gate oxide

    Publication Year: 1999 , Page(s): 390 - 392
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (58 KB)  

    The results of an investigation of time-dependent breakdown (TDDB) of intrinsic ultrathin gate oxide are presented for a wide range of oxide fields 4.6 View full abstract»

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  • Hydrogen-induced piezoelectric effects in InP HEMT's

    Publication Year: 1999 , Page(s): 393 - 395
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (55 KB)  

    In this letter, we have investigated hydrogen degradation of InP HEMT's with Ti/Pt/Au gates. We have found that V/sub T/ shifts negative after exposure to hydrogen, and exhibits an L/sub G/ and orientation dependence. We postulate that /spl Delta/V/sub T/ is at least in part due to the piezoelectric effect. Hydrogen exposure leads to the formation of TiH/sub x/, producing compressive stress in the gate. This stress induces a piezoelectric charge distribution in the semiconductor that shifts the threshold voltage. We have independently confirmed TiH/sub x/ formation under our experimental conditions through Auger measurements. Separate radius-of-curvature measurements have also independently confirmed that Ti/Pt films become compressively stressed relative to their initial state after H/sub 2/ exposure. View full abstract»

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  • Submicron transferred-substrate heterojunction bipolar transistors

    Publication Year: 1999 , Page(s): 396 - 398
    Cited by:  Papers (70)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (154 KB)  

    We report submicron transferred-substrate AlInAs/GaInAs heterojunction bipolar transistors (HBT's). Devices with 0.4-μm emitter and 0.4-μm collector widths have 17.5 dB unilateral gain at 110 GHz. Extrapolating at -20 dB/decade, the power gain cutoff frequency fmax is 820 GHz. The high fmax, results from the scaling of HBT's junction widths, from elimination of collector series resistance through the use of a Schottky collector contact, and from partial screening of the collector-base capacitance by the collector space charge. View full abstract»

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  • An analytical thermal noise model of deep submicron MOSFET's

    Publication Year: 1999 , Page(s): 399 - 401
    Cited by:  Papers (47)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (91 KB)  

    An analytical model for circuit simulation to describe the channel thermal noise in MOSFET's for all channel length down to deep submicron is presented and verified by measurements. Contrary to the thermal equilibrium assumption, this model includes the influence of the increasing electrical field with downscaling on the channel carrier (electron, hole) equivalent noise temperature. If not taken into account, simulation errors of up to 100% and more in the thermal noise of half micron transistors and below occur. View full abstract»

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  • A thermodynamic noise model for nonlinear resistors

    Publication Year: 1999 , Page(s): 402 - 404
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (49 KB)  

    A Gaussian white noise model for passive nonlinear resistors, valid in the linear quadratic current-voltage (I-V) approximation at zero bias, is suggested. Although approximative, the model, which has originally been developed by R.L. Stratonovich, is thermodynamically well founded. The model is applied to the shot noise of exponential diodes and tunnel junctions as well as to the thermal noise of JFET's and MOSFET's. Within the range of the linear-quadratic approximation, the results are in full agreement with the well-known device specific standard low frequency thermal and shot noise models for these devices. The model can he considered as a linear-quadratic short circuit noise current generalization of Nyquist's formula. View full abstract»

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  • Electrothermal oscillations of a PN junction operating in avalanche breakdown region

    Publication Year: 1999 , Page(s): 405 - 408
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (71 KB)  

    We consider a simple circuit composed of a diode operating in the avalanche breakdown region (ABR), a capacitor and a constant current source. Through a nonlinear analysis, we show the existence of oscillations caused by the combined action of thermal and electrical behaviors of the device. This analysis is confirmed by simulations and experiments. View full abstract»

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  • A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide

    Publication Year: 1999 , Page(s): 409 - 411
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (45 KB)  

    A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature. View full abstract»

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  • Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

    Publication Year: 1999 , Page(s): 412 - 414
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed significantly. The improvements can be attributed that NSB effectively increase the needed electrical fields for fast programming and erasing, respectively. Furthermore, the cycling endurance is improved considerably if NSB is applied for programming and erasing operation both. View full abstract»

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  • High field effect mobility deuterated amorphous silicon thin-film transistors based on the substitution of hydrogen with deuterium

    Publication Year: 1999 , Page(s): 415 - 417
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (135 KB)  

    The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550/spl deg/C in N/sub 2/ environment to expel all the hydrogen atoms out of the films, then the D/sub 2/ or H/sub 2/ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm/sup 2//V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm/sup 2//V-s. View full abstract»

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  • Dependence of Si pn junction perimeter leakage on the channel-stop boron dose and interlayer material

    Publication Year: 1999 , Page(s): 418 - 420
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (54 KB)  

    The effects of the channel-stop boron dose (CSB) on the perimeter leakage current (L/sub L/) of local oxidation of silicon (LOCOS)-isolated Si pn junction diodes were found to depend on the interlayer material used. The I/sub L/ of diodes having a SiO/sub 2/ interlayer slightly decreased in the low reverse voltage (V/sub r/) region and increased in the high V/sub r/ region with a higher CSB. This is attributed to the depletion layer reduction and carrier generation enhancement caused by the higher CSB. In contrast, the I/sub L/ of TEOS-BPSG interlayer diodes increased by one order of magnitude with a higher CSB. Such anomaly is explained by an inversion layer under the LOCOS oxide: it suppresses I/sub L/ by covering the carrier generation centers, but it is compensated by the higher CSB. View full abstract»

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  • A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition

    Publication Year: 1999 , Page(s): 421 - 423
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (88 KB)  

    We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFT's). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) oxide performed at 23/spl deg/C. Devices fabricated with the new process exhibit a lower leakage current and a better ON/OFF current ratio than non-LDD control devices. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be quite promising for future high-performance poly-Si TFT fabrication. View full abstract»

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  • Design and characterization of high-voltage self-clamped IGBT's

    Publication Year: 1999 , Page(s): 424 - 427
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB)  

    A new concept of field limiting ring (FLR) with variable ring widths is proposed for designing a high-voltage collector-gate clamped IGBT. An insulated gate bipolar transistor (IGBT) based on the concept has been designed and fabricated with a conventional IGBT process flow to provide a clamp voltage of 620 V. The dc and unclamped inductive switching (UIS) energy parameters of the IGBT are fully characterized for a temperature range of -40-150/spl deg/C. The new high-voltage self-clamped IGBT is to be primarily used in automotive ignition applications. View full abstract»

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  • 1.2 kV trench insulated gate bipolar transistors (IGBT's) with ultralow on-resistance

    Publication Year: 1999 , Page(s): 428 - 430
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB)  

    In this letter, we report the full development of 1.2 kV Trench IGBT's with ultralow on-resistance, latch-up free operation and highly superior overall performance when compared to state of the art IGBT's. The minimum forward voltage drop at the standard current density of 100 A/cm/sup 2/ was 1.1 V for nonirradiated devices and 2.1 V for irradiated devices. The maximum controllable current density was in excess of 1000 A/cm/sup 2/. View full abstract»

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  • A 475-V high-voltage 6H-SiC lateral MOSFET

    Publication Year: 1999 , Page(s): 431 - 433
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (78 KB)  

    High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm/sup 2//V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (/spl sim/0.29-0.77 /spl Omega/-cm/sup 2/) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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