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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Issue 7 • Date Jul 1999

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Displaying Results 1 - 14 of 14
  • Passive equivalence of chaos in Lorenz system

    Page(s): 876 - 878
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (96 KB)  

    In this paper we present a new simple controller for a chaotic system: the Lorenz equation. The controller design is based on a passive technique. The final structure of this controller has a linear feedback form. Using a passive method, we prove the stability of the closed loop system View full abstract»

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  • Analysis and compensation of two-pole amplifiers with a pole-zero doublet

    Page(s): 864 - 868
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    A simple representation of a two-pole amplifier with a pole-zero doublet is proposed which can be used in the compensation of transconductance amplifiers. The model is based on the consideration that a pole-zero doublet does not greatly modify the behavior of the closed-loop amplifier. Indeed, assuming an underdamped behavior we have found that the pole-zero doublet only affects the phase margin and, hence, it can accurately be accounted for by properly modifying the second pole of the original two-pole amplifier. Simulations on a two-stage transconductance amplifier show that such a model closely agrees with the time response of the real amplifier View full abstract»

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  • Robust synthesis for master-slave synchronization of Lur'e systems

    Page(s): 841 - 850
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    In this paper a method for robust synthesis of full static-state error feedback and dynamic-output error feedback for master-slave synchronization of Lur'e systems is presented. Parameter mismatch between the systems is considered in the synchronization schemes. Sufficient conditions for uniform synchronization with a bound on the synchronization error are derived, based on a quadratic Lyapunov function. The matrix inequalities from the case without parameter mismatch between the Lur'e systems remain preserved, but an additional robustness criterion must be taken into account. The robustness criterion is based on an uncertainty relation between the synchronization error bound and the parameter mismatch. The robust synthesis method is illustrated on Chua's circuit with the double scroll. One observes that it is possible to synchronize the master-slave systems up to a relatively small error bound, even in the case of different qualitative behavior between the master and the uncontrolled slave system, such as limit cycles and stable equilibria View full abstract»

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  • Analysis of bifurcation phenomena in a 3-cells hysteresis neural network

    Page(s): 851 - 857
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    This paper considers bifurcation phenomena in a simplified hysteresis neural network. The network consists of three cells and has three control parameters. We have discovered that the simple system exhibits various attractors: stable equilibria, periodic orbits, and chaos. Since the system is piecewise linear, the return map and Lyapunov exponents are calculated by using the piecewise exact solution. Using the mapping procedure, the bifurcation mechanism of stable equilibria and three kinds of bifurcation mechanisms of periodic orbits have been clarified. In addition, chaos has been analyzed by using Lyapunov exponents of the return map View full abstract»

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  • The energy bounds in RC circuits

    Page(s): 869 - 871
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    Exponentially decreasing upper and lower bounds for the energy of a general RC network are derived. They give simply computable bounds for the global delay time View full abstract»

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  • Stability and margin of stability tests for multidimensional filters

    Page(s): 806 - 809
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    In this paper we give simplified proofs of the stability and the margin of stability criteria of Zeheb and Walach for n-dimensional recursive digital filters. We base our proofs on the method of Lagrange multipliers. Both the stability and margin of stability questions are converted into the problem of locating the zeros of a system of polynomial equations. These systems can then be solved using Buchberger's algorithm for computing the Groebner basis of a polynomial ideal View full abstract»

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  • Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors

    Page(s): 861 - 864
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    A low-voltage BiCMOS four-quadrant multiplier using triode-region transistors is presented, this circuit has been fabricated in a 1.0 μm BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.6 V with the linearity error of less than 2%. The total harmonic distortion is less than 2% with an input range up to ±0.6 V. The measured -3-dB bandwidth of this proposed BiCMOS multiplier is about 10 MHz. This circuit is expected to be useful in low-voltage analog signal-processing applications View full abstract»

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  • Irregular terms in the impulse response of a multiconductor lossy transmission line

    Page(s): 788 - 805
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    Linear multiconductor transmission lines can be effectively represented in the time domain as a dynamic multiport through the describing input and transfer impulse responses. Unfortunately, these responses cannot be analytically evaluated for the most general case of lossy lines. In addition, they cannot even be evaluated numerically due to the presence of irregular terms such as Dirac pulses, functions that actually approximate Dirac pulses, and functions of the type 1/√t. Nevertheless, all these irregular terms can be isolated from the regular ones. This paper proposes an analytical method to evaluate exactly the irregular terms. This method is based on the perturbation theory of the spectrum of symmetric matrices and can be easily and effectively applied to the most general case of frequency-dependent lossy multiconductor lines. Once the irregular parts of the impulse responses are known, it is possible to evaluate accurately the regular ones through simple numerical methods, as shown through some examples View full abstract»

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  • Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits

    Page(s): 779 - 787
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    A procedure for the determination of an optimum set of testable components in the fault diagnosis of analog linear circuits is presented. The proposed method has its theoretical foundation in the testability concept and in the canonical ambiguity group concept. New considerations relevant to the existence of unique solution in the k-fault diagnosis problem of analog linear circuits are presented, and examples of application of the developed procedure are considered by exploiting a software package based on symbolic analysis techniques View full abstract»

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  • Effects of the deviation of element values in a ring of three and four coupled Van der Pol oscillators

    Page(s): 827 - 840
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    This paper investigates the effect of element value deviation on the degenerate mode in rings of three and four coupled Van der Pol oscillators. By using the averaging method, we elucidate that the element value deviation has different effects on the rings of three and four coupled oscillators. Namely, for the ring of three coupled oscillators, two single modes which bifurcate from the twofold degenerate mode in the symmetric system can be synchronized when they are close, but they lose synchronization and a quasiperiodic oscillation appears when they are separated to some extent. In contrast, for the ring of four coupled oscillators, the two single modes cannot be synchronized, even if they are close. However, in some rare cases they can be synchronized when they are separated to some extent. We confirm these results of the averaging method by both computer simulation and experiments View full abstract»

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  • Separation conditions and approximation of continuous-time approximately finite memory systems

    Page(s): 820 - 826
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    We consider causal time-invariant nonlinear input-output maps that take a set of locally pth-power integrable functions into a set of real-valued functions, and we give criteria under which these maps can be uniformly approximated arbitrarily well using a certain structure consisting of a not-necessarily-linear dynamic part, followed by a nonlinear memoryless section that may contain sigmoids or radial basis functions, etc. In our results, certain separation conditions, of the kind associated with the Stone-Weierstrass theorem, play a prominent role. Here they emerge as criteria for approximation, not just sufficient conditions under which an approximation exists. As an application of the results and for p=2 we show that system maps of the type addressed can be uniformly approximated arbitrarily well by certain doubly finite Volterra-series approximants if and only if these maps have approximately finite memory and satisfy certain continuity conditions View full abstract»

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  • A systematic approach to circuit design and analysis: classification of two-VCCS circuits

    Page(s): 810 - 819
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    This paper discusses a systematic approach to the design and analysis of circuits, using a transconductor or voltage controlled current source (VCCS) as a building block. It is shown that two independent Kirchhoff relations among the VCCS voltages and currents play a crucial role in establishing a unique transfer function in two-port circuits with two VCCSs. A class of two VCCS circuits is defined, which can be subdivided into three main classes and 14 subclasses, based on different imposable sets of two Kirchhoff relations. The classification is useful for circuit synthesis and analysis, as it reveals all the basically different ways to exploit two VCCS's, and allows for a unified analysis of classes of circuits. To exemplify this, all complementary metal-oxide-semiconductor (CMOS) V-I converter kernels, based on two matched MOS transistor (MOST)-VCCSs, are generated and analyzed with respect to distortion. It is shown that dozens of published transconductor circuits can be classified in only four classes, with essentially different distortion behavior View full abstract»

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  • A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS

    Page(s): 857 - 861
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    Certain logic functions such as the control units of VLSI processors are difficult to implement by random logic. Since the programmable logic arrays (PLAs) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. We present a low-power high-speed complementary-metal-oxide semiconductor (CMOS) circuit implementation of NOR-NOR PLA using a single-phased clock. Buffering static NAND gates are inserted between the NOR planes to erase the racing problem and shorten the duration of glitches such that the dynamic power is reduced in addition to the low static power dissipation, no ground switch, no charge sharing, and zero offset View full abstract»

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  • Low delta-I noise CMOS circuits based on differential logic and current limiters

    Page(s): 872 - 876
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    Switching noise is becoming an important constraint in mixed signal design. In this paper we present an approach to implement combinational circuits that generate low levels of delta-I noise by obtaining a trapezoidal current waveform shape. We use a differential logic (ECDL) together with current limiters to implement a 4×4 multiplier. We present the results of the simulation of this multiplier and the comparison with the static complementary-metal-oxide semiconductor (CMOS) implementation View full abstract»

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