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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 6 • Date Jun 1999

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Displaying Results 1 - 22 of 22
  • The impact of induced gate noise when simultaneously power and conjugate noise-matching MOS transistors

    Publication Year: 1999 , Page(s): 842 - 844
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (100 KB)  

    A method for simultaneously power matching and conjugate noise matching a MOS transistor for radio frequency applications is presented in this paper. Experimental results from a 0.6 μm nMOS transistor show that the magnitude of input reactance equals the optimum noise reactance (i.e., Xin=Xopt). Using this result, the author provides a method that can be used to match the ... View full abstract»

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  • A blind fractionally spaced equalizer using higher order statistics

    Publication Year: 1999 , Page(s): 755 - 764
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (260 KB)  

    In this paper, we introduce a new blind fractionally spaced equalizer based on the fourth-order statistics of the input symbol sequence. The input symbol sequence is assumed to come from an independent identically distributed finite alphabet with nonzero fourth-order cumulants. We formulate the equalizer as a column vector and compute it by simultaneously diagonalizing a set of matrices obtained f... View full abstract»

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  • Multiple operating points in a CMOS log-domain filter

    Publication Year: 1999 , Page(s): 705 - 710
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (412 KB)  

    A second order bandpass filter was designed by converting a conventional bipolar junction transistor-based log-domain filter circuit to its weak-inversion CMOS equivalent. When biased as designed, the filter performed as expected, but the integrated circuit at times self-biased to an unintended operating point, rendering the circuit useless. This behavior is related to the positive feedback loops ... View full abstract»

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  • Pulse-based 2-D motion sensors

    Publication Year: 1999 , Page(s): 677 - 687
    Cited by:  Papers (29)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (812 KB)  

    We present two compact CMOS integrated circuits for computing the two-dimensional (2-D) local direction of motion of an image focused directly onto the chip. These circuits incorporate onboard photoreceptors and focal plane motion processing. With fully functional 14×13 and 12×13 implementations consuming less than 50 μW per pixel, we conclude that practical pixel resolutions of at ... View full abstract»

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  • Decorrelating (DECOR) transformations for low-power digital filters

    Publication Year: 1999 , Page(s): 776 - 788
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (360 KB)  

    Decorrelating transformations (referred to as DECOR transformations) to reduce the power dissipation in digital filters are presented in this paper. The transfer function and/or the input is decorrelated such that fewer bits are required to represent the coefficients and inputs. Thus, the size of the arithmetic units in the filter is reduced, thereby reducing the power dissipation. The DECOR trans... View full abstract»

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  • A 200-MHz CMOS I/Q downconverter

    Publication Year: 1999 , Page(s): 808 - 810
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (192 KB)  

    This CMOS in-phase/quadrature (I/Q) downconverter circuit is based on a modified sampling architecture which permits very precise I/Q phase and amplitude balance across the entire 200-MHz bandwidth of operation. At a radio frequency of 201 MHz, the downconverter uses a local oscillator sampling rate of 40 MHz and an intermediate frequency of 1 MHz. The circuit is implemented in a 0.5-μm process... View full abstract»

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  • Efficient training of neural gas vector quantizers with analog circuit implementation

    Publication Year: 1999 , Page(s): 688 - 698
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (312 KB)  

    This paper presents an algorithm for training vector quantizers with an improved version of the neural gas model, and its implementation in analog circuitry. Theoretical properties of the algorithm are proven that clarify the performance of the method in terms of quantization quality, and motivate design aspects of the hardware implementation. The architecture for vector quantization training incl... View full abstract»

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  • A generalized prediction method for modified memory-based high throughput VLC decoder design

    Publication Year: 1999 , Page(s): 742 - 754
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (576 KB)  

    Variable-length code (VLC) is the most popular data-compression technique which has been used in many data-compression standards, such as JPEG, MPEG-2, and H.263. In this paper, we present a new memory-based tree-search algorithm and very large scale integration architecture for VLC decoders which can achieve very high decoding throughput performance. Different coding tables can be implemented by ... View full abstract»

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  • Effect of switch resistance on the SC integrator settling time

    Publication Year: 1999 , Page(s): 810 - 816
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (260 KB)  

    Using general feedback theory, a model is developed for the switched-capacitor integrator. This model is then used to analyze the effects of sampling and feedback switch resistances on the integrator settling time. If the frequency corresponding to the sampling time constant is less than five times the frequency of the second pole of the amplifier, the integrator settling time will be degraded. Th... View full abstract»

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  • Circuit requirements of a direct conversion paging receiver

    Publication Year: 1999 , Page(s): 802 - 807
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (192 KB)  

    Circuit requirements of a direct-conversion FLEX paging receiver with the zero-crossing interpolation demodulator are derived by means of high-level simulation. Impacts of the limitations on noise and nonlinearity characteristics of the radio frequency (RF) stage, the in-phase and quadrature-phase mismatch, and the local oscillator frequency drift are analyzed relative to the degradation of the bi... View full abstract»

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  • Sigma-delta ADC with reduced sample rate multibit quantizer

    Publication Year: 1999 , Page(s): 824 - 828
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (156 KB)  

    Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to exten... View full abstract»

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  • New multifunction OTA-C biquads

    Publication Year: 1999 , Page(s): 820 - 824
    Cited by:  Papers (47)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (116 KB)  

    Some novel multifunction biquadratic filters, each of which employs two to three operational transconductance amplifiers and two capacitors, are presented. Each proposed circuit offers the following advantageous features: realization of different biquadratic filter signals from the same configuration, no requirements for component-matching conditions, employment of only two capacitors, control of ... View full abstract»

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  • Efficient architectures to recover the regularized least squares solution

    Publication Year: 1999 , Page(s): 828 - 831
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (348 KB)  

    Several practical applications are concerned with the identification of the least squares (LS) solution. The objective is to attain this solution accurately and efficiently while conserving resources. The computational and storage requirements to determine the LS solution by any iterative procedure become prohibitively large as the problem dimensions grow. This work presents some architectures bas... View full abstract»

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  • A novel adaptive mismatch cancellation system for quadrature IF radio receivers

    Publication Year: 1999 , Page(s): 789 - 801
    Cited by:  Papers (90)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (328 KB)  

    This paper investigates and resolves in-phase/quadrature phase (I/Q) imbalances between the input paths of quadrature IF receivers. These mismatches along the paths result in the image interference aliasing into the desired signal band, thus reducing the dynamic range and degrading the performance of the receivers. I/Q errors occur because of gain and phase imbalances between quadrature mixers. Th... View full abstract»

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  • Wave digital filter structures for high-speed narrow-band and wide-band filtering

    Publication Year: 1999 , Page(s): 726 - 741
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (352 KB)  

    Wave digital filter (WDF) structures for high-speed narrow-band and wide-band filtering are introduced. The narrow-band filter is composed of a periodic model filter and one or several, possibly periodic, masking filters in cascade. Lattice and bireciprocal lattice WDF filters are used for the model and masking filters, respectively. The wide-band filter consists of a narrow-band filter in paralle... View full abstract»

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  • Design of low-error fixed-width multipliers for DSP applications

    Publication Year: 1999 , Page(s): 836 - 842
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (328 KB)  

    In this work, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2 n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multi... View full abstract»

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  • Analog circuit performance and process scaling

    Publication Year: 1999 , Page(s): 711 - 725
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (308 KB)  

    With newer CMOS processes, minimum transistor dimensions decrease and the supply voltage steadily gets lower. This trend is driven by the performance of digital systems: their level of performance (speed) increases while at the same time the cost (power consumption and die area) decreases. However, the performance of analog or mixed-signal circuits in newer CMOS generations does not necessarily im... View full abstract»

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  • Noise analysis for sampling mixers using stochastic differential equations

    Publication Year: 1999 , Page(s): 699 - 704
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (128 KB)  

    We analyze three different sources of noise in a sampling mixer working at radio frequency (RF) or intermediate frequency. External RF and intrinsic noise are analyzed using conventional frequency domain methods. External local oscillator (LO) noise is analyzed in the time domain by solving a stochastic differential equation. We are able to take into account the time varying aspect of the LO noise... View full abstract»

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  • Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

    Publication Year: 1999 , Page(s): 661 - 676
    Cited by:  Papers (100)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (440 KB)  

    The performance of continuous-time (CT) delta-sigma modulators (ΔΣM's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a... View full abstract»

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  • Semi-infinite linear programming: a unified approach to digital filter design with time- and frequency-domain specifications

    Publication Year: 1999 , Page(s): 765 - 775
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    Using the recently developed semi-infinite linear programming techniques and Caratheodory's dimensionality theory, we present a unified approach to digital filter design with time and/or frequency-domain specifications. Through systematic analysis and detailed numerical design examples, we demonstrate that the proposed approach exhibits several salient features compared to traditional methods: 1) ... View full abstract»

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  • A low-voltage rail-to-rail CMOS V-I converter

    Publication Year: 1999 , Page(s): 816 - 820
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (176 KB)  

    This paper presents CMOS low-voltage rail to-rail voltage-to-current (V-I) converters which could be used as basic building blocks to construct low-voltage current-mode analog very large scale integration (VLSI) circuits. In the circuit, an n-type V-I converter cell is connected in parallel with its p-type counterpart to achieve common-mode rail to-rail operation. A linear differential relationshi... View full abstract»

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  • Limit-cycle oscillations in a log-domain-based filter

    Publication Year: 1999 , Page(s): 832 - 836
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (128 KB)  

    A circuit is presented for a class-AB fully differential log-domain parallel resonator based on a capacitively loaded gyrator. It is shown that if floating rather than shunt capacitive loads are used, the circuit is stable for small stimuli, but can be triggered into steady-state limit-cycle oscillations by large enough transient inputs. The nature of the instability is explored and it is shown ho... View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope