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Advanced Packaging, IEEE Transactions on

Issue 2 • Date May 1999

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Displaying Results 1 - 16 of 16
  • New high-density multilayer technology on PCB

    Page(s): 116 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    Demand has recently increased for very high-density packaging substrates for high-pin-count area array chips. Our new high-density multilayer technology on printed circuit board (PCB), named deposited substrate on laminate (DSOL) satisfies this demand. An important feature of the DSOL is dielectric fabrication, which uses a new photosensitive material; an aromatic fluorene unit bonded epoxy acrylate resin. The fluorene based resin has interesting properties such as good electrical properties, low curing temperature (160°C) for a heat-resistant resin (glass transition temperature, Tg=230°C), low coefficient of the thermal expansion (40 ppm), and excellent via hole resolution. Very fine and high-aspect-ratio (>1.0) via holes were formed through exactly the same process steps as those used for a conventional photosensitive epoxy resin; baking, exposure, and development with an aqueous alkaline solution. Another important feature is the technology, that patterns fine-pitch Cu conductors using a semi-additive process with a sputtering method. The DSOL made 40 μM very fine pitch Cu conductors on large laminates (330 mm×400 mm) possible, because this process was composed of flash wet etching of only 0.3 μm thick sputtered thin-films. We have successfully developed a high-density packaging substrate for high-pin-count (4000 pins) area array application specific integrated circuit (ASIC) chips View full abstract»

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  • Manufacturing experience with high performance mixed dielectric circuit boards

    Page(s): 153 - 159
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB)  

    A wide range of advanced dielectric materials are available for use in high speed digital and RF/microwave printed circuit boards (PCBs). These materials present new challenges in the manufacturing process, especially when they are combined in mixed or unbalanced structures. The properties of these materials are reviewed, and their impact on manufacturing in various product applications is discussed View full abstract»

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  • Processing thick multilevel polyimide films for 3-D stacked memory

    Page(s): 189 - 199
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    This paper discusses thick polyimide film processing for a three-dimensional (3-D) semiconductor chip-stacking application. The formation of a complex, multilevel via structure is demonstrated. The issues that arise in forming these vias relate to apply, develop, profile modification, and integration. Apply issues include “outgassing” defects, edge-bead effects, as well as the planarity and leveling of both resist and polyimide over deep-via structures. Develop issues pertain to the implementation of a thick resist process that increases the structural integrity of the resist and controls its breakage, and to a vacuum bake before applying resist, which reduces solvent absorption into the resist. Profile modification issues include rounding via edges while minimizing bulk polyimide loss and maintaining image-size control. Developer attack of the metal pads during wet processing is discussed and a solution is proposed. Finally, additional process-integration issues relating to polyimide-to-metal adhesion and composite stress levels of the multilayer thick films are presented View full abstract»

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  • Packaging-compatible high Q microinductors and microfilters for wireless applications

    Page(s): 207 - 213
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    To meet requirements in mobile communication and microwave integrated circuits, miniaturization of the inductive components that many of these systems require is of key importance. At present, active circuitry is used which simulates inductor performance and which has high Q-factor and inductance; however, such circuitry has higher power consumption and higher potential for noise injection than passive inductive components. An alternate approach is to fabricate integrated inductors, in which lithographic techniques are used to pattern an inductor directly on a substrate or a chip. However, integrated inductors can suffer from low Q-factor and high parasitic effects due to substrate proximity. To expand the range of applicability of integrated microinductors at high frequency, their electrical characteristics, especially quality factor, should be improved. In this work, integrated spiral microinductors suspended (approximately 60 μm) above the substrate using surface micromachining techniques to reduce the undesirable effect of substrate proximity on the inductor performance are investigated. The fabricated inductors have inductances ranging from 15-40 nH and Q-factors ranging from 40-50 at frequencies of 0.9-2.5 GHz. Microfilters based on these inductors are also investigated by combining these inductors with integrated polymer filled composite capacitors View full abstract»

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  • Evolution of engineering change and repair technology in high performance multichip modules at IBM

    Page(s): 129 - 135
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    In multichip modules (MCMs), engineering changes (EC) are required for both repair of defective chip to chip connections within the module, as well as modification of electrical connections for module performance optimization. With the recent use of complementary metal-oxide-semiconductor (CMOS) chips in IBM's latest generation of mainframe machines, EC design has been modified to accommodate chips with a much higher number of signal I/Os. Using the previous design methodology of connecting each signal C4 to an EC pad, a large area of the top surface of the module would be required for EC features. This would force increased chip-to-chip wiring length and impact module performance. In addition, larger size MCMs would be required, driving up cost. The new EC approach utilizes top surface thin film wiring in the X and Y directions, which is not pre-connected to any signal C4 pads. The approach used to make desired EC connections is described. New processes were developed to make micro-connections to customize an EC connection, CMOS based MCMs have more than 5× the signal I/Os per chip compared to bipolar devices. As a result of the evolution in EC technology, CMOS chip based MCMs have been successfully designed, built, tested and debugged quickly. They are being used in IBM's latest generation mainframe machines View full abstract»

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  • On resonant effects in multilayer RF/microwave printed circuit board applications

    Page(s): 200 - 206
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    Multilayer printed-circuit boards (PCB's) are nowadays widely used in high-frequency technology applications. While their small dimensions, compact design and low cost are an obvious advantage, the impact of full-wave phenomena such as electromagnetic coupling, resonance or leakage increases substantially as the used frequency spectrum shifts toward and beyond the upper UHF band and the L-band (1-2 GHz). Two types of PCB structures exhibiting resonant properties are considered in this paper: PCB shielding covers and large split-ground conducting plates. These structures can cause narrow-band (resonant) cross-talk. Their behavior is studied by both numerical and analytical approaches, and simple techniques to predict possible resonant coupling are proposed View full abstract»

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  • Evaluation of closed-form crosstalk models of coupled transmission lines

    Page(s): 174 - 181
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    Closed-form crosstalk models used for the estimation of near and far end crosstalk voltages between two parallel transmission lines are evaluated. The quantitative validity ranges, in terms of transmission line length and coupling strength, of the crosstalk models are presented. It is shown that the accuracy of the commonly used closed-form crosstalk models deteriorates as the increase of the coupling strength and the line length View full abstract»

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  • An innovative technique for packaging power electronic building blocks using metal posts interconnected parallel plate structures

    Page(s): 136 - 144
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    Power electronics building blocks (PEBBs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. At the Center for Power Electronics Systems, we developed a topology for a basic building block-a two-switch two-diode half-bridge converter in totem-pole configuration with built-in gate-driver and protection circuitry, fiber-optic receiver/transmitter interface, and soft-switching capability. Based on the topology, a series of prototype modules, with 600 V, 3.3 kW rating, were fabricated using an innovative packaging technique developed for the program-metal posts interconnected parallel plate structure (MPIPPS). This new packaging technique uses direct attachment of bulk copper, not wire-bonding of fine aluminum wires, for interconnecting power devices. Electrical performance data of the packaged devices show that an air-cooled 15 kW inverter, operating from 400 V dc bus with 20 kHz switching frequency can be constructed by integrating three prototype modules, which is almost double what could be achieved with commercially packaged devices of the same rating View full abstract»

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  • Hermetic-equivalent packaging of GPS MCM-L modules for high reliability avionics applications

    Page(s): 145 - 152
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    Results are presented of comparative reliability testing of multichip modules (MCM's) fabricated with laminate substrates, and protected with various bare-die coatings. The demonstration MCM's included two design versions (flip-chip and wire-bond) of the digital portion of global positioning system (GPS) receiver multichip modules. This paper summarizes the results for the wire-bonded constructions. Standard encapsulants and new inorganic coatings (Dow Coming's ChipSeal(R) hermetic coating materials') were evaluated in environmental stress exposures corresponding to high reliability avionics applications. Full wafer probe testing was performed both before and after the supplemental ChipSeal processing and dip-chip wafer bump processing steps. ChipSeal and flip-chip wafer processing steps were shown to cause no yield degradation on wafer lots of five different IC types used in the overall program. The environmental test results demonstrate that MCM-L units with bare die packaging can be designed for very robust reliability applications such as military and other high reliability avionics View full abstract»

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  • RF flip-module BGA package

    Page(s): 111 - 115
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    We recently described a flip-chip package with integrated thin-film inductors and capacitors in a VCO tank circuit of a single chip GSM transceiver integrated circuit (IC). By embedding the passive components in a Si-on-Si substrate, we eliminated spurious resonances that were caused by the parasitics of the original 64-TQFP IC package. However, compared with the bare die, the resultant Si-on-Si structure is larger in all dimensions due to the inclusion of a flip-chip mounted transceiver IC and a surface-mount varactor. We have developed a novel BGA package structure with a hole milled in the center to accommodate the silicon-on-silicon assembly. The interconnections rely exclusively on flip-chip solder technology. To verify that the package does not degrade the performance of the RF circuits, we have performed electromagnetic field simulations to extract critical inductance and capacitance parameters. Parasitic inductances of the original TQFP and the new packages are comparable due to their similar dimensions. None the less, a major advantage of the new package structure is that it permits the integration of key passive components inside the package where they are unaffected by package parasitic impedances View full abstract»

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  • Overmold technology applied to cavity down ultrafine pitch PBGA package

    Page(s): 123 - 128
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    The transfer molding technology is normally used for leadframe type packages and chip-up plastic ball grid array (PBGA) packages. This technology has been applied to cavity down PBGA packages where, normally, a liquid epoxy is dispensed by a needle in the cavity in order to cover the device and gold wires without exceeding the solder ball height plane. The new encapsulation approach using transfer molding process as well as the debug/qualification method and results using an ultrafine pitch wirebond PBGA process will be described View full abstract»

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  • Influence of a floating plane on effective ground plane inductance in multilayer and coplanar packages

    Page(s): 182 - 188
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    The impact of a floating metal layer on the effective ground plane inductance has been investigated in both multilayer (ground planes) and coplanar (ground conductors) packages. For the multilayer case, both thick and thin film geometries were examined, and the results were compared to a thin film coplanar configuration. It was seen that the floating plane actually increases the ground plane inductance in the multilayer case and decreases the ground plane inductance in the lead frame case. Examining the current density in the floating and ground plane and the ground's partial self-inductance and ground-signal partial mutual inductance give a detailed explanation for this phenomenon View full abstract»

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  • A CMOS image sensor module applied for a digital still camera utilizing the TAB on glass (TOG) bonding method

    Page(s): 160 - 165
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    The world's smallest (105×55×20 mm) and lightest (130 g) digital still camera has been developed, in which a 330 K pixel complementary metal-oxide-semiconductor (CMOS) image sensor chip is used as an image sensor. The authors have developed a new thinner and smaller image sensor module, called tape automated bonding (TAB) on glass (TOG) module, using the anisotropic conductive paste (ACP) interconnection method. The TOG production process was established by obtaining optimum bonding conditions for both optical glass bonding and CMOS chip bonding to the TAB tape. The bonding conditions including sufficient bonding margins, were mainly studied. The TOG module obtained good imaging properties, It also has a high reliability such as thermal cycle test (-40 to +110°C/30 min, 2000 cycles) and the high temperature storage test (60°C, 90% RH, 3000 h). The stable production process was confirmed by fabricating an automatic bonding machine View full abstract»

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  • The contact resistance and reliability of anisotropically conductive film (ACF)

    Page(s): 166 - 173
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    The effect of bonding pressure on the electrical and mechanical properties of anisotropic conductive film (ACF) joint using nickel particles and metal-coated polymer ball-filled ACFs was investigated. The contact resistance decreases as the bonding pressure increases. Contact resistance of ACF is determined by the contact area change between particles and contact substrates. Electrical conduction through the pressure engaged contact area between conductive particles and conductor substrates is the main conduction mechanism in ACF interconnection. In addition, environmental effects on contact resistance and adhesion strength such as thermal aging, high temperature/humidity aging and temperature cycling were also investigated. Interestingly, the contact resistances of the excessively bonded samples deteriorated more than those of optimally bonded ones. Increasing contact resistance and decreasing adhesion strength after harsh environmental tests were mainly due to the loss of contact by thermal stress effect and moisture absorption, and also partially due to the formation of metal oxide on the conductive particles View full abstract»

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  • Surface graft copolymerization enhanced adhesion of an epoxy-based printed circuit board substrate (FR-4) to copper

    Page(s): 214 - 220
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    The lamination of surface modified printed circuit board (PCB) substrate, FR-4(R), from argon plasma pretreatment and UV-induced graft copolymerization with glycidyl methacrylate (GMA), to copper foil was carried out at elevated temperature and in the presence of an epoxy adhesive. The structure and chemical composition of the graft copolymerized surfaces and interfaces of the glass fiber-reinforced and epoxy-based FR-4 substrates were studied by X-ray photoelectron spectroscopy (XPS). The effects of the plasma pretreatment time, the UV illumination time, as well as the curing temperature, on the adhesion strength between the FR-4 substrate and copper were investigated. The assemblies involving GMA graft copolymerized FR-4, or the FR-4-GMA/epoxy resin/Cu assemblies, exhibited a significantly higher interfacial adhesion strength and reliability, in comparison to those assemblies in which only epoxy adhesive alone was used. The enhanced adhesion in the assemblies involving GMA graft copolymerized substrate arises from the fact that the covalently tethered GMA graft chains on the FR-4 surface can become covalently incorporated into the epoxy resin, resulting in the toughening of the epoxy matrix and increased interaction with copper View full abstract»

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  • Frequency response characteristics of reference plane effective inductance and resistance [IC packaging]

    Page(s): 221 - 229
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    A method which uses the partial element equivalent circuit (PEEC) method and electrical network theory to solve for the effective impedance matrix of reference planes is presented. The convergence and accuracy of the method are checked. The frequency responses of the effective inductance (Leff(f)) and resistance (Reff(f)) of reference plane are discussed. The effects of current redistribution and the skin effect on Leff(f) and R eff(f) are discussed. The effect of number of sinks and sources is examined View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering