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IEEE Transactions on Computers

Issue 4 • Date Apr 1999

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Displaying Results 1 - 6 of 6
  • COFTA: hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance

    Publication Year: 1999, Page(s):417 - 441
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (964 KB)

    Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis of an embedded system is the process of partitioning, mapping, and scheduling its specification into hardware and software modules to meet performance, cost, reliability, and availability goals. In this paper, we address the problem of hardware... View full abstract»

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  • Detecting exitory stuck-at faults in semimodular asynchronous circuits

    Publication Year: 1999, Page(s):442 - 448
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Beerel (1994) showed that semimodular asynchronous circuits are totally self-checking with respect to multiple output stuck-at faults that are nonexitory and nonsubstitutional. We show that, in circuits with atomic gate implementations, it is possible to ensure that all exitory multiple output stuck-at faults will cause the circuit to halt View full abstract»

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  • Fault-containment in cache memories for TMR redundant processor systems

    Publication Year: 1999, Page(s):386 - 397
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Cache data errors read by a processor may cause CPU control flow error and force the system to enter a CPU-cache reintegration process in redundant processor systems. The reintegration process degrades the system performance and reliability. To reduce the occurrences of such an event, we propose a real-time error recovery scheme that provides effective fault-containment for data errors in cache me... View full abstract»

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  • Minimizing conflicts between vector streams in interleaved memory systems

    Publication Year: 1999, Page(s):449 - 456
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    The performance of a vector processor accessing vectors placed in memory is strongly dependent on the conflicts produced in the memory subsystem. These conflicts delay the task of the functional units. There can be conflicts between elements of the same vector and between elements of different vector streams. It is known that the presence of the last kind of conflicts is the main cause of cycles l... View full abstract»

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  • Greedy, prohibition, and reactive heuristics for graph partitioning

    Publication Year: 1999, Page(s):361 - 385
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1172 KB)

    New heuristic algorithms are proposed for the Graph Partitioning problem. A greedy construction scheme with an appropriate tie-breaking rule (MIN-MAX-GREEDY) produces initial assignments in a very fast time. For some classes of graphs, independent repetitions of MIN-MAX-GREEDY are sufficient to reproduce solutions found by more complex techniques. When the method is not competitive, the initial as... View full abstract»

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  • Configuration of locally spared arrays in the presence of multiple fault types

    Publication Year: 1999, Page(s):398 - 416
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    The bulk of results for the performance of configuration architectures treat the case of failed processors, but neglect switches that are stuck open or closed. By contrast, the present work characterizes this multivariate problem in the presence of either iid or clustered faults. Suppose that the designer wishes to assure, with high probability, a fault free s×t array. If local sparing is us... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org