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Electron Device Letters, IEEE

Issue 11 • Date Nov. 1989

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Displaying Results 1 - 14 of 14
  • Electrical characterization of a JFET-accessed GaAs dynamic RAM cell

    Page(s): 477 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB)  

    A complete one-transistor dynamic RAM cell in GaAs is discussed. Read and write operations is monitored by observing the capacitance of the storage node. Storage times on the order of a few seconds are obtained at room temperature with an activation energy slightly less than half the zero-temperature bandgap.<> View full abstract»

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  • Limitation of spacer thickness in titanium salicide ULSI CMOS technology

    Page(s): 481 - 483
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    The isolation integrity of various gate-spacer thicknesses in 15-20- mu m-wide MOS devices with and without titanium salicide is discussed. The gate-spacer thickness varies from 25 to 100 nm. Experimental results show that for Ti salicided devices with only a 25-nm-thick gate spacer, a broad spectrum of gate-drain (source) breakdown voltages, at a leakage current level of 2 mu A, is measured in the range of 1.5 to 10 V. Using a specific gate-spacer tester with a total gate-spacer perimeter near 10 cm in length, the statistical data taken over 100 tested chips show that as the thickness of the gate spacer is reduced to less than 50 nm, the gate leakage increases to 10/sup -9/ A under a gate bias equal to 5 V. The leakage of the thin gate spacer is attributed to the formation of Ti-rich oxide during the Ti self-aligned silicide process, which degrades the isolation integrity and generates a leakage path. The implications of this leakage mechanism for ULSI technologies are discussed.<> View full abstract»

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  • Sub-300-ps CBL circuits

    Page(s): 484 - 486
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    Advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a 'free' epi-base lateral p-n-p (cutoff frequency=300 MHz only), and deep trench isolation are discussed. Using 1.2- mu m design rules and a modified push-pull output stage, a gate delay (fan-in=3) of 278 ps was obtained at a DC current of 30 mu A/gate. The low power-delay product underlies the speed and power potential of CBL as an attractive practical approach to bipolar complementary transistor logic.<> View full abstract»

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  • Submicrometer salicide CMOS devices with self-aligned shallow/deep junctions

    Page(s): 487 - 489
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (267 KB)  

    The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5- mu m physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices.<> View full abstract»

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  • Microfabricated scanning tunneling microscope

    Page(s): 490 - 492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB)  

    A scanning tunneling microscope (STM) with dimensions 1000 mu m*200 mu m*8 mu m constructed by planar microfabrication techniques is discussed. The device incorporates a piezoelectric actuator capable of three-dimensional motion for scanning and control of the tunneling gap spacing. Operation of the device has been successfully demonstrated by imaging the surface of a graphite sample with atomic resolution.<> View full abstract»

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  • Microwave characterization of a resistive-gate MESFET oscillator

    Page(s): 493 - 495
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    Measurements of microwave oscillations in resistive-gate MESFET contiguous-domain oscillator devices are discussed. Oscillation frequencies in the ranges from 22 to 30 GHz and 37 to 42 GHz are observed independently of the device length, and frequency can be tuned during operation by varying the source-to-gate voltage. Evidence suggests that the observed signals are harmonics of a fundamental signal in the range from 11 to 15 GHz. While the possibility that conventional transit-time Gunn domain propagation is occurring in this frequency range cannot be ruled out, the fact that frequency is independent of channel length suggests that contiguous domains are forming, at least in the longer devices. Because of its structure, the resistive-gate MESFET oscillator can be easily incorporated into MESFET integrated circuits for MMIC (monolithic microwave integrated circuit) applications.<> View full abstract»

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  • A new technique for determining the generation lifetime profile in thin semiconductor films with application to silicon-on-insulator (SOI) substrates

    Page(s): 496 - 499
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    A differential technique which uses reverse-biased current-voltage (I-V) and capacitance-voltage (C-V) measurements on a p-n junction or a Schottky barrier diode for determining the generation lifetime profile in thin semiconductor films is discussed. It is shown that the bias-independent current can be eliminated by this differential technique. Furthermore, any error caused by field-enhanced current can be estimated. This method has been used to determine the generation lifetime profile in thin silicon epitaxial film grown on SIMOX substrates.<> View full abstract»

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  • An empirical model for the L/sub eff/ dependence of hot-carrier lifetimes of n-channel MOSFETs

    Page(s): 500 - 502
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB)  

    An empirical model that describes the dependence of hot-carrier lifetime on the effective channel length of an n-channel MOSFET, allowing the estimation of the lifetimes of transistors of a given length based on data from a limited number of channel lengths, is presented. The model takes into account the localization of hot-carrier induced damage and shows that the size of the damaged region relative to the total length of the transistor is important in determining the effect of hot-carrier-damage-induced transistor characteristics. The results are integrated into two commonly used equations for hot-carrier lifetimes of MOSFETs of a given channel length under DC operation. The model is experimentally verified for MOSFETs of effective channel lengths between 0.45 and 2.7 mu m.<> View full abstract»

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  • Small-geometry, high-performance, Si-Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors

    Page(s): 503 - 505
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    Si-Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors (HBTs) with very heavily doped bases, fabricated using electron-beam lithography to obtain very small feature sizes, are discussed. Emitter, base, and collector epitaxial layers were grown in situ in a lamp-heated, chemical-vapor-deposition reactor. Transistors with common-emitter current gain of approximately 50 and f/sub t/ of about 28 GHz have been obtained. Analysis indicates that the frequency response is limited by parasitic resistances and capacitances in the simple demonstration structure used, rather than by the intrinsic device characteristics. Simple ring oscillators have been fabricated using HBTs in the inverse-active mode of operation.<> View full abstract»

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  • A new self-aligned AlGaAs/GaAs HBT based on refractory emitter and base electrodes

    Page(s): 506 - 507
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (222 KB)  

    A self-alignment technique for AlGaAs/GaAs heterojunction bipolar transistors (HBTs) using refractory metal film, W, as the emitter and base electrodes is presented. A nonalloyed contact formation combined with selective reactive ion etching of W or WSi/sub x/ against GaAs and SiO/sub 2/ produces a self-aligned structure. An emitter contact that is thermally stable is obtained by using a Zn diffusion process to make the extrinsic base contact layer. An f/sub T/ value as high as 82 GHz was obtained. The self-alignment technique combined with the Zn diffusion process will achieve a much higher f/sub T/ if a thinner base HBT structure is used.<> View full abstract»

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  • Isolated emitter AlGaAs/GaAs HBT integrated with emitter-down HI/sup 2/L technology

    Page(s): 508 - 510
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    A process that integrates isolated-emitter heterojunction bipolar transistors (HBTs) with common-emitter HBTs in the emitter-down epi structure on n/sup +/ substrates is discussed. Overgrowth of the epi onto a p/sup -/ implanted region results in back-to-back diodes for approximately 12-V vertical isolation. Isolated transistors are used in emitter-follower output buffers for heterojunction injection logic (HI/sup 2/L) ring oscillators, demonstrating the integration of the two transistor types.<> View full abstract»

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  • A high-gain, low-noise 1/2- mu m pulse-doped pseudomorphic HEMT

    Page(s): 511 - 513
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    A 1/2- mu m gate-length pulse-doped pseudomorphic high-electron-mobility transistor (HEMT) grown by MBE, which exhibits a current-gain cutoff frequency of 62 GHz, is discussed. The maximum available gain cutoff frequency was greater than 150 GHz. A minimum noise figure of 0.85 dB and associated gain of 14 dB were measured at 10 GHz. Tuned small-signal gain in a waveguide-to-microstrip test fixture at 44 GHz was 7.6 dB. When the HEMT was tuned for power, 260 mW/mm with 5-dB gain and 17% power-added efficiency were obtained at 44 GHz. These results suggest that a 1/2- mu m pseudomorphic HEMT is a viable candidate for Q-band applications.<> View full abstract»

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  • Two-step annealing technique for leakage current reduction in chemical-vapor-deposited Ta/sub 2/O/sub 5/ film

    Page(s): 514 - 516
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    A capacitor technology developed to obtain extremely thin Ta/sub 2/O/sub 5/ dielectric film with an effective SiO/sub 2/ film thickness down to 3 nm (equivalent to 11 fF/ mu m/sup 2/) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta/sub 2/O/sub 5/ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O/sub 3/) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O/sub 2/) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps.<> View full abstract»

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  • BiMOS transistors: merged bipolar/sidewall MOS transistors

    Page(s): 517 - 519
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible.<> View full abstract»

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