IEEE Design & Test of Computers

Issue 5 • Oct. 1989

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Displaying Results 1 - 6 of 6
  • DFT Expert: designing testable VLSI circuits

    Publication Year: 1989, Page(s):8 - 19
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (819 KB)

    A set of expert-system modules for designing easily testable VLSI circuits called DFT Expert is described. DFT Expert operates at the register-transfer level of circuit description, classifying circuit components into data transporters (DTs) and data processors (DPs). It identifies DPs and DTs, selects a test method, configures global design for test (DFT), and generates test schedules. DFT Expert... View full abstract»

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  • A data structure for fast region searches

    Publication Year: 1989, Page(s):20 - 28
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (709 KB)

    Bucketing, also known as fixed cells, is a data structure that is especially suitable for queries that cover small windows. However, this technique is not efficient if objects are long and narrow, such as wires. Also, as more objects are added, the efficiency of the query process may suffer. The authors describe a dynamic bucketing structure that maintains a two-level director structure and uses a... View full abstract»

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  • VLSI design and CAD technology in Korea

    Publication Year: 1989, Page(s):29 - 39
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    An overview is given of Korean VLSI and CAD technology, which did not develop naturally as it did in more advanced countries. Korean engineers had no electronic systems developed domestically for studying bipolar and MOS IC design. Consequently, they had to apply reverse engineering to the problem, which slowed development considerably. In 1982, the Korean government initiated the national project... View full abstract»

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  • Logic simulation engines in Japan

    Publication Year: 1989, Page(s):40 - 49
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (835 KB)

    A description is given of HAL II and SP, ultra-high-speed logic simulation engines for use in verifying large computer logic designs. Both use parallel processor architecture with a maximum configuration of 64 processors. The resulting simulation speed is a thousand times faster than that of conventional software logic simulators run on a mainframe. HAL II and SP, which can simulate a system with ... View full abstract»

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  • Ideas: a tool for VLSI CAD

    Publication Year: 1989, Page(s):50 - 57
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (634 KB)

    The authors describe the Ideas integrated design automation system being developed in India. Ideas is based on a new high-level hardware description language, called Ideal (integrated design automation language), which incorporates several features that allow it to model both event-driven and demand-driven behavior. Ideas is built on an object-oriented kernel and consists of a text-graphics front-... View full abstract»

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  • Test counting: a tool for VLSI testing

    Publication Year: 1989, Page(s):58 - 77
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2777 KB)

    The authors present a technique, called test counting, for analyzing the testing requirements imposed on a combinational network in the form of a set of stuck-at faults to be detected. By solving a large set of mathematical inequalities, called constraints, test counting determines that certain pairs of faults cannot be test simultaneously. The result is a set of mutually independence faults, no t... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty