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IEE Proceedings - Computers and Digital Techniques

Issue 1 • Jan 1999

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Displaying Results 1 - 9 of 9
  • Technology mapping for simultaneous gate and interconnect optimisation

    Publication Year: 1999, Page(s):21 - 31
    Cited by:  Papers (1)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1124 KB)

    A technology mapping approach is presented which performs simultaneous gate and interconnect optimisation. For area optimisation, a cost function is proposed which takes into account both gate area and interconnect area to minimise the total chip area after layout. New techniques are proposed to estimate the interconnect cost and to calculate the gate cost more accurately. For delay optimisation, ... View full abstract»

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  • Fuzzy time point compatibility reasoning for microprocessor systems

    Publication Year: 1999, Page(s):68 - 76
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (828 KB)

    Time range reasoning and fuzzy time point reasoning have been proposed and implemented for microprocessor systems diagnosis. These approaches provide effective temporal constraint reasoning based on two primitive mechanisms: the constraint satisfaction and the constraint propagation. Through the reasoning process, the occurrence time of a microprocessor system event is determined with respect to a... View full abstract»

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  • PTM: technology mapper for pass-transistor logic

    Publication Year: 1999, Page(s):13 - 19
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (532 KB)

    The pass-transistor mapper (PTM) is reported; this is a logic synthesis tool specifically designed for pass-transistor-based logic library that has only three basic cells. It exploits the close relationship between a binary decision diagram (BDD) representation of logic and the structure of pass-transistor logic cells to ensure efficient mapping. BDD-variable order is achieved a genetic through al... View full abstract»

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  • Graph-based detailed router for hierarchical field-programmable gate arrays

    Publication Year: 1999, Page(s):57 - 67
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (864 KB)

    The paper presents a detailed routing algorithm for the hierarchical field-programmable gate arrays (HFPGAs). This algorithm is two phases. First performed in a multilevel transformed into a HFPGA is single-level HFPGA to find the initial routing results. The initial routing problem is reduced to the graph colouring and Steiner-tree problems. Two types of routing structure, disjointed and overlapp... View full abstract»

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  • Self-checking synchronous controller design

    Publication Year: 1999, Page(s):9 - 12
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (332 KB)

    Efficient models are introduced for totally self-checking/code disjoint (TSC/CD) and strongly fault-secure/strongly code disjoint (SFS/SCD) synchronous controller models. These models are based on two low-cost, modular, TSC edge-triggered and error-propagating CD flip-flops. Properties of the proposed synchronous controller models are proven. The design procedure for these models and their proper ... View full abstract»

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  • Design and implementation of fault-tolerant and cost effective crossbar switches for multiprocessor systems

    Publication Year: 1999, Page(s):50 - 56
    Cited by:  Papers (2)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (528 KB)

    Two general crossbar switch models are proposed: the modified one-sided crossbar switch and the ripple K one-sided crossbar switch. They both balance cost and reliability, where cost is expressed in terms of crosspoint count or area. The two-sided crossbar switch and the one-sided crossbar switch are two cases of these structures. These structures provide choices for compromising structures betwee... View full abstract»

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  • Nondeterministic AND-EXOR minimisation by using rewrite rules and simulated annealing

    Publication Year: 1999, Page(s):1 - 8
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (672 KB)

    A new AND-EXOR minimisation procedure is presented, which is able to optimise both completely and incompletely specified logic functions, with one or several outputs. It is based on the use of an annealing process to select the rewrite rule that should be applied to the current expression of the function to be minimised. Unlike other reported procedures, this procedure implements a nondeterministi... View full abstract»

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  • Performance evaluation of TCP/IP protocol implementations in end systems

    Publication Year: 1999, Page(s):32 - 40
    Cited by:  Papers (2)  |  Patents (17)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1648 KB)

    Conventional protocol implementation suffers in data-moving operations, limiting the maximum throughput. Experiments have measured the large incidence of these operations in a conventional protocol such as TCP/IP running in a Unix environment. To overcome this drawback protocol implementations have been proposed involving a processor and network interface that could share the same storage buffer. ... View full abstract»

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  • Haar spectra-based entropy approach to quasi-minimisation of FBDDs

    Publication Year: 1999, Page(s):41 - 49
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (776 KB)

    An information theoretic approach, to exploit the additional degree of freedom associated with don't cares of incompletely specified Boolean functions, is applied to quasi-minimisation of free binary decision diagrams (FBDDs). The concept of entropy and equivocation is formulated through paired Haar spectra of incompletely specified Boolean functions. The likelihood metric expressed in terms of se... View full abstract»

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