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Circuits, Devices and Systems, IEE Proceedings -

Issue 6 • Date Dec. 1998

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Displaying Results 1 - 11 of 11
  • Packaging impact on switching noise in high-speed digital systems

    Page(s): 446 - 452
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    Owing to the ever-increasing clock frequency in digital circuits and systems, simultaneous switching noise (SSN), caused by fast rise/fall pulse edges in combination with parasitic inductance in the power supply distribution network, is becoming a severe problem in many high-speed digital system designs. It is quantitatively shown that the influence of SSN, which is negligible when the rise/fall time is long (>5 ns), becomes a critical factor, limiting system performance in the subnanosecond rise time region. Based on theoretical analyses and computational simulations in respect to various packaging techniques, technical solutions and design guidelines for reducing SSN are summarised. View full abstract»

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  • New method to bias CMOS cascode amplifiers

    Page(s): 440 - 442
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    The authors present a new method for biasing AC-coupled cascode amplifiers. The proposed design allows the correct DC biasing with a single reference signal as well as a single power supply. A start-up circuit is added for correctly biasing the cascode amplifier at power on. SPICE simulations based on a 0.8 μm CMOS technology are included View full abstract»

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  • Modulo multipliers using polynomial rings

    Page(s): 443 - 445
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    The performance of many DSP chips depends to a great extent on their multiply-accumulate (MAC) speed. In this direction, the use of residue arithmetic has been proved to enhance the speed of multiplier units. One approach has been to convert all multiplication operations to addition, thereby speeding up the whole operation. This was made possible by defining a logarithmic transform for the integers in a finite field, more specifically in a prime field GF(p). The author extends this approach to the case of polynomial rings (quotient rings), thereby providing more choices for the selection of moduli in RNS multipliers View full abstract»

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  • State variable synthesis of single-resistance-controlled grounded capacitor oscillators using only two CFOAs: additional new realisations

    Page(s): 415 - 418
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    The authors report eight new `two-CFOA-two-grounded-capacitor-three-resistor' single-resistance-controlled oscillators (SRCO) and the results of experimental investigations of the fourteen SRCOs of this class (including six introduced in an earlier communication) View full abstract»

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  • Modelling output waveform and propagation delay of a CMOS inverter in the submicron range

    Page(s): 402 - 408
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    An accurate, analytical model is presented for the evaluation of the CMOS inverter delay in the submicron regime. Following an exhaustive analysis of the inverter operation, accurate expressions of the output response to an input ramp are derived, which result in the analytical calculation of the propagation delay. These expressions are valid for all the inverter operation regions and input waveform slopes, and take into account the influences of the short-circuit current and the gate-drain coupling capacitance. The effective output transition time of the inverter is determined, in order to map the real output waveform to a ramp waveform for the model to be applicable to CMOS gate chains. The results are in very good agreement with SPICE simulations View full abstract»

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  • High-impedance voltage bias circuit for MOS amplifiers

    Page(s): 437 - 439
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    An MOS integrated circuit that delivers an equal DC bias voltage to several independent nodes through impedances in the range 1010 -1012 Ω is reported. One application of this circuit is that of providing bias to each stage of an iterative stage amplifier where high impedance is desired to allow small coupling capacitors between stages View full abstract»

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  • Analysis of interpolation waveforms in time-averaging interpolative digital-to-analogue converters

    Page(s): 389 - 395
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    An analytical model is introduced for the study of interpolation waveforms in time-averaging interpolative digital-to-analogue converters (DACs). This analytical model reveals some important phenomena related to the interpolation process, and it can be used to determine the effects of varying individual interpolation waveforms on the overall performance of DACs. This allows strategies to be developed for minimising interpolation noise. The model can also be used to enhance the performance of many interpolation schemes. Examples of some minimisation strategies are presented, including practical results View full abstract»

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  • Smith chart formulation of performance characterisation for a microwave transistor

    Page(s): 419 - 428
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    A scattering parameter theory of the performance characterisation for a bilateral transistor is developed, where mismatching at the input port Vi is considered as a degree of freedom, and its combination with noise and gain is mapped as circles in the Γin-plane. Stability analysis is based on the unconditionally stable working area (USWA) concept, and all possible USWA configurations are determined by the necessary and sufficient conditions. For each USWA configuration, the constrained maximum stable gain GTmax and its termination couple (Ts, Γ L) are expressed as functions of the input VSWR Vi, noise figure F and the scattering S and noise N parameter vectors. Furthermore, the possible incompatible cases for the (F, Vi, GTmax) triplets are determined by their necessary and sufficient conditions. A computer program based on this formulation is developed, and cross-relations among the (F, Vi, GTmax) triplets have been utilised in obtaining the performance contours at an operating frequency and bias condition View full abstract»

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  • High-performance transimpedance formulation for MESFET- and HBT-based monolithic microwave integrated circuits

    Page(s): 429 - 436
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    Analysis of amplifier and feedback combinations leads to the conclusion that the transimpedance configuration offers the opportunity of constant-bandwidth operation. As an example, a transimpedance amplifier based on shunt feedback around a current-gain amplifying element is described, which achieves gain-bandwidth independence at microwave frequencies. Full foundry layout simulation for circuits based on both MESFETs and HBTs indicates that an optical receiver front-end amplifier designed on these principles will exhibit gain-bandwidth independence through the GHz region, with very low sensitivity to photodiode capacitance View full abstract»

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  • Efficient digital sweep oscillator with extremely low sweep rates

    Page(s): 409 - 414
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    The performance of the Pedersen digital sweep oscillator is improved using a new technique which is intended to improve the sweep rates so that they can reach extremely low ranges without the need of increasing look-up table width. The proposed technique is shown to be very efficient in increasing the effective table length, and hence, the number of generated samples during the sweep time. The sweep rate is improved by storing and reading the sine and cosine components of two sweep functions that are not harmonically related, and then evaluating the sweep signal of the phase difference. Better performance can be achieved by using the trigonometric identity method as demonstrated. There are no limitations on the time-bandwidth product of the proposed structure. Performance calculations and simulation results are given to support the analytically claimed results and demonstrate the performance View full abstract»

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  • Passive lossless snubbers for DC/DC converters

    Page(s): 396 - 401
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    A general passive lossless snubber cell is proposed for use in DC/DC converters. The snubber is to suppress the turn-on loss of a MOSFET resulting from the reverse recovery current of the freewheeling diode. Energy recovery is achieved since the energy absorbed by the snubber during turn-on can be delivered to the output during turn-off. The simple structure and the absence of active components and resistors make this snubber a good alternative to a conventional RCD snubber or an active snubber. As an example, a boost converter equipped with the snubber is analysed. A 1 kW, 100 kHz prototype is implemented in the laboratory, and efficiency of 97% has been measured. Six basic non-isolated DC/DC converters equipped with the proposed snubber cell are also illustrated View full abstract»

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