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IEE Proceedings E - Computers and Digital Techniques

Issue 2 • Mar 1988

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Displaying Results 1 - 5 of 5
  • Heuristic algorithm for the minimisation of generalised Boolean functions

    Publication Year: 1988, Page(s):108 - 116
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (568 KB)

    Generalised Boolean functions are useful in the design of programmable logic arrays. In this paper a heuristic algorithm suitable to minimise such functions is presented. The algorithm generates an irredundant cover by using a local approach to select generalised prime implicants. A benefit of such a method is that the preliminary generation of the set of all the generalised prime implicants is no... View full abstract»

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  • High-level microprogramming support embedded in silicon

    Publication Year: 1988, Page(s):73 - 81
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (748 KB)

    The design and implementation of SJ16, a 16-bit microprogrammable processor chip, is presented. Novel features include a new regenerative carry scheme, a systolic stack control mechanism, and microprogram sequencing based upon the microAPL high-level microprogramming methodology. Relevant CMOS design issues are discussed. View full abstract»

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  • Sequential block interleave coding of two-tone facsimile data

    Publication Year: 1988, Page(s):95 - 107
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (812 KB)

    A new method of compression called sequential block interleave coding (SBIC), is presented which features a fixed-rate output and exhibits a strong immunity to transmission errors. The method encodes block-pairs of binary image data over a field of blocks without the need for codebooks. By initially scrambling blocks the field size requirement can be considerably decreased, thereby reducing the pr... View full abstract»

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  • Economic approach to fault-tolerant synchronisation

    Publication Year: 1988, Page(s):82 - 86
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (328 KB)

    Previous solutions to the problem of synchronising fault-tolerant multiprocessor systems require either 3t+1 processors (for t-fault-tolerance) or else multiple rounds of messages with unforgeable digital signatures. These solutions are too expensive for small microprocessor-style control systems. The paper shows that simple constraints on the physical design of the communication links permit a mu... View full abstract»

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  • Systematic design strategy for concurrent error diagnosable iterative logic arrays

    Publication Year: 1988, Page(s):87 - 94
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (452 KB)

    An in-depth study of RESO (re-computing with shifted operands) theory is conducted which leads to the extension of the theory so that efficient CED designs for two-dimensional array structures and complex functions can be achieved. Based on the enhanced version of RESO, a systematic design strategy has been developed to allow the designer to take advantage of knowledge of fault configurations. View full abstract»

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