By Topic

Computers, IEEE Transactions on

Issue 3 • Date Mar 1999

Filter Results

Displaying Results 1 - 8 of 8
  • Efficient techniques for dynamic test sequence compaction

    Page(s): 323 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. Three simulation-based techniques for dynamic compaction of test sequences are described. The first technique uses a fault simulator to remove test vectors from the test sequence generated by a test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in a partially-specified test sequence in order to increase the number of faults detected by the sequence. The third technique uses test sequences provided by the test generator as seeds in a genetic algorithm, and better sequences are evolved that detect more faults. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches using combinations of the three techniques View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast static compaction algorithms for sequential circuit test vectors

    Page(s): 311 - 322
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states and some states are frequently revisited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and if sufficient conditions are met for them. Contrary to the previously proposed methods, where multitudes of fault simulations are required, the techniques described in this paper require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A comparative analysis of cache designs for vector processing

    Page(s): 331 - 344
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    This paper presents an experimental study on cache memory designs for vector computers. We use an execution-driven simulator to evaluate vector cache performance of a set of application programs from Perfect Club and SPEC92 benchmark suites. Our simulation results uncover a few important facts which were unknown before: First of all, the prime-mapped cache that we newly proposed shows great performance potential in vector processing environment. Because of its conflict-free property, the prime-mapped cache performs significantly better than conventional cache designs for all applications considered. Second, performance results on the benchmarks indicate that data locality in vector processing does exist, although the effects of line size, associativity, replacement algorithm, and prefetching scheme on cache performance are very different from what has been commonly believed. A medium size vector cache (e.g., 128 Kbytes) eliminates the necessity for a large number of interleaved memory banks in vector computers. Our experiments show that the vector computer that has a medium size prime-mapped cache with small cache line size and limited amount of prefetching provides significant speedup over conventional vector computers without cache. Performance results reported in this paper can also provide guidance to general-purpose computer designers to enhance cache performance for numerical applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient tree cache coherence protocol for distributed shared memory multiprocessors

    Page(s): 352 - 360
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    Directory schemes have long been used to solve the cache coherence problem for large scale shared memory multiprocessors. In addition, tree-based protocols have been employed to reduce the directory size and the invalidation latency for a large degree of data sharing in the system. However, the existing tree-based protocols involve a very high communication overhead for maintaining a balanced tree, especially when the degree of data sharing is low. This paper presents a new tree-based cache coherence protocol which is a hybrid of the limited directory and the linked list schemes. By utilizing a limited number of pointers in the directory, the proposed protocol connects the nodes caching a shared block in a tree fashion without incurring any communication overhead. In addition to the low communication overhead, the proposed scheme also possesses the advantages of the existing bit-map and tree-based linked list protocols, namely, scalable memory requirement and logarithmic invalidation latency. We evaluate the performance of our protocol by running four applications on the Proteus execution-driven simulator. Our simulation results show that the performance of the proposed protocol is very close to that of the full-map protocol View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wide-sense nonblocking Clos networks under packing strategy

    Page(s): 265 - 284
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    In this paper, we study wide-sense nonblocking conditions under packing strategy for the three-stage Clos network, or υ(m, n, r) network. Wide-sense nonblocking networks are generally believed to have lower network cost than strictly nonblocking networks. However, the analysis for the wide-sense nonblocking conditions is usually more difficult. Moore proved that a υ(m, n, 2) network is nonblocking under packing strategy if the number of middle stage switches m⩾[3/2n]. This result has been widely cited in the literature, and is even considered as the wide-sense nonblocking condition under packing strategy for the general υ(m, n, r) networks in some papers. In fact, it is still not known that whether the condition m⩾[3/2n] holds for υ(m, n, r) networks when r⩾3. In this paper, we introduce a systematic approach to the analysis of wide-sense nonblocking conditions for general υ(m, n, r) networks with any r value. We first translate the problem of finding the nonblocking condition under packing strategy for a υ(m, n, r) network to a set of linear programming problems. We then solve this special type of linear programming problems and obtain a closed form optimum solution. We prove that the necessary condition for a υ(m, n, r) network to be nonblocking under packing strategy is m⩾[(2-1/F2r-1)n] where F2r-1 is the Fibonacci number. In the case of n⩽F 2r-1, this condition is also a sufficient nonblocking condition for packing strategy. We believe that the systematic approach developed in this paper can be used for analyzing other wide-sense nonblocking control strategies as well View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2-by-n hybrid cellular automata with regular configuration: theory and application

    Page(s): 285 - 295
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    This paper introduces a new class of two-dimensional linear cellular automata and derives a number of their properties. A recursive relation is proved which enables the characteristic polynomial to be efficiently calculated, and minimal cost, maximal length generators of this type are listed for sizes up to 500. A theoretical analysis of the two vector transition properties of the cellular automata is given and it is shown that, for testing sequential faults over a set of standard benchmarks, the two-dimensional cellular automata perform, on average, better than one-dimensional linear hybrid cellular automata, and much better than linear finite shift registers View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Spectral analysis of Boolean functions as a graph eigenvalue problem

    Page(s): 345 - 351
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    Several problems in digital logic can be conveniently approached in the spectral domain. In this paper we show that the Walsh spectrum of Boolean functions can be analyzed by looking at algebraic properties of a class of Cayley graphs associated with Boolean functions. We use this idea to investigate the Walsh spectrum of certain special functions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On a new Boolean function with applications

    Page(s): 296 - 310
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    Consider a hypercube of 2n points described by n Boolean variables and a subcube of 2m points, m⩽n. As is well-known, the Boolean function with value 1 in the points of the subcube can be expressed as the product (AND) of n-m variables. The standard synthesis of arbitrary functions exploits this property. We extend the concept of subcube to the more powerful pseudocube. The basic set is still composed of 2m points, but has a more general form. The function with value 1 in a pseudocube, called pseudoproduct, is expressed as the AND of n-m EXOR-factors, each containing at most m+1 variables. Subcubes are special cases of pseudocubes and their corresponding pseudoproducts reduce to standard products. An arbitrary Boolean function can be expressed as a sum of pseudoproducts (SPP). This expression is in general much shorter than the standard sum of products, as demonstrated on some known benchmarks. The logical network of an n-bit adder is designed in SPP, as a relevant example of application of this new technique. A class of symmetric functions is also defined, particularly suitable for SPP representation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au