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IEEE Transactions on Computers

Issue 3 • Date Mar 1999

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Displaying Results 1 - 8 of 8
  • Efficient techniques for dynamic test sequence compaction

    Publication Year: 1999, Page(s):323 - 330
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. Three simulation-based techniques for dynamic compaction of test sequences are described. The first technique uses a fault simulator to remove test vectors from the test sequence generated by a test generator if the vectors a... View full abstract»

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  • Spectral analysis of Boolean functions as a graph eigenvalue problem

    Publication Year: 1999, Page(s):345 - 351
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Several problems in digital logic can be conveniently approached in the spectral domain. In this paper we show that the Walsh spectrum of Boolean functions can be analyzed by looking at algebraic properties of a class of Cayley graphs associated with Boolean functions. We use this idea to investigate the Walsh spectrum of certain special functions View full abstract»

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  • 2-by-n hybrid cellular automata with regular configuration: theory and application

    Publication Year: 1999, Page(s):285 - 295
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    This paper introduces a new class of two-dimensional linear cellular automata and derives a number of their properties. A recursive relation is proved which enables the characteristic polynomial to be efficiently calculated, and minimal cost, maximal length generators of this type are listed for sizes up to 500. A theoretical analysis of the two vector transition properties of the cellular automat... View full abstract»

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  • Fast static compaction algorithms for sequential circuit test vectors

    Publication Year: 1999, Page(s):311 - 322
    Cited by:  Papers (41)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states and some states are frequently revisited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and if sufficient conditions are met for ... View full abstract»

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  • A comparative analysis of cache designs for vector processing

    Publication Year: 1999, Page(s):331 - 344
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    This paper presents an experimental study on cache memory designs for vector computers. We use an execution-driven simulator to evaluate vector cache performance of a set of application programs from Perfect Club and SPEC92 benchmark suites. Our simulation results uncover a few important facts which were unknown before: First of all, the prime-mapped cache that we newly proposed shows great perfor... View full abstract»

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  • Wide-sense nonblocking Clos networks under packing strategy

    Publication Year: 1999, Page(s):265 - 284
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    In this paper, we study wide-sense nonblocking conditions under packing strategy for the three-stage Clos network, or υ(m, n, r) network. Wide-sense nonblocking networks are generally believed to have lower network cost than strictly nonblocking networks. However, the analysis for the wide-sense nonblocking conditions is usually more difficult. Moore proved that a υ(m, n, 2) network is n... View full abstract»

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  • An efficient tree cache coherence protocol for distributed shared memory multiprocessors

    Publication Year: 1999, Page(s):352 - 360
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Directory schemes have long been used to solve the cache coherence problem for large scale shared memory multiprocessors. In addition, tree-based protocols have been employed to reduce the directory size and the invalidation latency for a large degree of data sharing in the system. However, the existing tree-based protocols involve a very high communication overhead for maintaining a balanced tree... View full abstract»

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  • On a new Boolean function with applications

    Publication Year: 1999, Page(s):296 - 310
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Consider a hypercube of 2n points described by n Boolean variables and a subcube of 2m points, m⩽n. As is well-known, the Boolean function with value 1 in the points of the subcube can be expressed as the product (AND) of n-m variables. The standard synthesis of arbitrary functions exploits this property. We extend the concept of subcube to the more powerful pseudocube. T... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org