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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • Apr 1999

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Displaying Results 1 - 11 of 11
  • Filling algorithms and analyses for layout density control

    Publication Year: 1999, Page(s):445 - 462
    Cited by:  Papers (60)  |  Patents (65)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density crit... View full abstract»

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  • Non-Hanan routing

    Publication Year: 1999, Page(s):436 - 444
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    This work presents a Steiner tree construction procedure, maximum delay violation Elmore routing tree, to meet specified sink arrival time constraints. It is shown that the optimal tree requires the use of non-Hanan points. The procedure works in two phases: a minimum-delay Steiner Elmore routing tree is first constructed using a minor variant of the Steiner Elmore routing tree procedure, after wh... View full abstract»

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  • Partitioning using second-order information and stochastic-gain functions

    Publication Year: 1999, Page(s):421 - 435
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB)

    A probability-based partitioning algorithm, PROP, was introduced in [8] that achieved large improvements over traditional “deterministic” iterative-improvement techniques like Fidducia-Mattheyses (FM) and Krishnamurthy's look-ahead (LA) algorithm. While PROP's gain function has a greater futuristic component than PM or LA, it incorporates spatially local information-only information on... View full abstract»

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  • A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

    Publication Year: 1999, Page(s):475 - 483
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a timing... View full abstract»

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  • An algorithm for determining repetitive patterns in very large IC layouts

    Publication Year: 1999, Page(s):494 - 501
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the s... View full abstract»

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  • Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing

    Publication Year: 1999, Page(s):406 - 420
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    In this paper we formulate three classes of optimization problems: the simple, monotonically constrained, and bounded Cong-He (CH)-programs. We reveal the dominance property under the local refinement (LR) operation for the simple CH-program, as well as the general dominance property under the pseudo-LR operation for the monotonically constrained CH-program and the extended-LR operation for the bo... View full abstract»

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  • Nostradamus: a floorplanner of uncertain designs

    Publication Year: 1999, Page(s):389 - 397
    Cited by:  Papers (9)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Floorplanning is an early phase in chip planning. It provides information on approximate area, delay, power, and other performance measures. Careful floorplanning is, thus, of extreme importance. In many applications, while a good floorplan is needed, the information about all modules is not available, or even worse, part of the provided information is inaccurate. Examples of such applications are... View full abstract»

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  • Critical area computation via Voronoi diagrams

    Publication Year: 1999, Page(s):463 - 474
    Cited by:  Papers (29)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    In this paper, we present a new approach for computing the critical area for shorts in a circuit layout. The critical area calculation is the main computational problem in very large scale integration yield prediction. The method is based on the concept of Voronoi diagrams and computes the critical area for shorts (for all possible defect radii, assuming square defects) accurately in O(n log n) ti... View full abstract»

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  • Sequence-pair approach for rectilinear module placement

    Publication Year: 1999, Page(s):484 - 493
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    With the recent advent of deep sub-micron technology and new packaging schemes such as multichip modules, integrated circuit components are often not rectangular. Most existing block placement approaches, however, only deal with rectangular blocks, resulting in inefficient area utilization. New approaches which can handle arbitrarily shaped blocks are essential to achieve high-performance design. ... View full abstract»

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  • Greedy wire-sizing is linear time

    Publication Year: 1999, Page(s):398 - 405
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this paper, we consider GWSA for continuous wire sizing. We prove that GWSA converges linearly to the optimal solution, which implies that the run time of GWSA is linear with respect to the number of wire segments for any fixed ... View full abstract»

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  • Device-level early floorplanning algorithms for RF circuits

    Publication Year: 1999, Page(s):375 - 388
    Cited by:  Papers (6)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric features-wire bends, precise length, planarity, etc., we suggest a new layout strategy for these circuits: early floorplanning at the device level. This paper develop... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu