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Solid-State Circuits, IEEE Journal of

Issue 3 • Date March 1999

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Displaying Results 1 - 19 of 19
  • Introduction to the Special Issue on the 1998 Custom Integrated Circuits Conference

    Page(s): 266 - 267
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    Freely Available from IEEE
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  • MDSP-II: a 16-bit DSP with mobile communication accelerator

    Page(s): 397 - 404
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    This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the Global System for Mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on chip to accelerate the execution of the key operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-μm triple-layer metal CMOS process on a 9.7×9.8 mm2 silicon area and was operated up to 50 MHz clock frequency View full abstract»

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  • A multistage amplifier technique with embedded frequency compensation

    Page(s): 339 - 347
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    A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-μm n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V/μs average slew rate with 40 pF load View full abstract»

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  • A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset

    Page(s): 415 - 420
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    A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper amplifiers is discussed. The amplifier features a total gain of 77±0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV/√Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-μm single-poly CMOS process View full abstract»

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  • Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates

    Page(s): 367 - 371
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    The performance and reliability of NMOSFET asymmetric lightly doped drain (LDD) devices (with no LDD on the source side) are compared with those of conventional LDD devices. At a fixed Vdd, asymmetric LDD devices exhibit higher Idsat and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower Vdd while higher Idsat is retained. For the same hot-carrier lifetime, ring oscillators with NMOSFET asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power. The hot-carrier reliability of inverter, NAND, and NOR structures with asymmetric and conventional LDD devices is also simulated and compared View full abstract»

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  • A low-power, high-performance, 1024-point FFT processor

    Page(s): 380 - 387
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    This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 μm (Lpoly=0.6 μm) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 μs while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate View full abstract»

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  • Mismatch shaping for a current-mode multibit delta-sigma DAC

    Page(s): 331 - 338
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    Mismatch shaping allows the use of multibit quantization in delta-sigma analog-to-digital converters and digital-to-analog converters (DAC's) since it noise-shapes the error caused by static element mismatch in a multibit DAC. In this paper, mismatch-shaping techniques for low-pass delta-sigma (ΔΣ) modulators are reviewed, and a mismatch-shaping technique for bandpass ΔΣ modulators is described. The dynamic error caused by frequent element switching is identified as a major source of error in a current-mode DAC with a continuous-time output. Modifying the mismatch-shaping algorithm to account for this effect yields a continuous-time ΔΣ DAC that is insensitive to both element mismatch and element switching dynamics. Experimental results confirm the effectiveness of the proposed techniques View full abstract»

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  • CMOS technology characterization for analog and RF design

    Page(s): 268 - 276
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    The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's “digital” technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution. This paper describes a set of characterization vehicles that can be employed to quantify the analog behaviour of active and passive devices in CMOS processes, in particular, properties that are not modeled accurately by SPICE parameters. Test structures and circuits are introduced for measuring speed, noise, linearity, loss, matching, and dc characteristics View full abstract»

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  • A Nyquist-rate pixel-level ADC for CMOS image sensors

    Page(s): 348 - 356
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    A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm2. It achieves 10×10 μm2 pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively View full abstract»

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  • Reducing switching activity on datapath buses with control-signal gating

    Page(s): 405 - 414
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    This paper presents a technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on buses. The focus of the technique is on achieving effective power savings with minimal overhead. When a bus is not going to be used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. The “observability don't-care condition” of a bus is defined to detect unnecessary switching activity on the bus. This condition is used to gate control signals going to the bus-driver modules so that switching activity on the module inputs does not propagate to the bus. A methodology for automatically synthesizing gated control signals from the register transfer level description of a design is presented. The technique has very low area, delay, power, and designer effort overhead. It was applied to one of the integer execution units of a 64-bit, two-way superscalar RISC microprocessor. Experimental results from running various application programs on the microprocessor show an average of 26.6% reduction in dynamic switching power in the execution unit, with no increase in critical path delay and negligible area overhead View full abstract»

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  • On-chip analog signal generation for mixed-signal built-in self-test

    Page(s): 318 - 330
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    A new method for generating analog signals with very low complexity and hardware requirements has recently been introduced. It consists of periodically reproducing short optimized bitstreams recorded from the output of a sigma-delta modulator. In this paper, various types of signals generated using the bitstream approach are discussed. Two different silicon implementations are presented, and their performance is analyzed through experimental results. Various ways in which the generators can be used are also demonstrated. Emphasis is placed on the simplicity of the design process and its compact implementation, which are crucial considerations when implementing a built-in self-test strategy View full abstract»

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  • A new scalable VLSI architecture for Reed-Solomon decoders

    Page(s): 388 - 396
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    A very-large-scale integration architecture for Reed-Solomon (RS) decoding is presented that is scalable with respect to the throughput rate. This architecture enables given system specifications to be matched efficiently independent of a particular technology. The scalability is achieved by applying a systematic time-sharing technique. Based on this technique, new regular, multiplexed architectures have been derived for solving the key equation and performing finite field divisions. In addition to the flexibility, this approach leads to a small silicon area in comparison with several decoder implementations published in the past. The efficiency of the proposed architecture results from a fine granular pipeline scheme throughout each of the RS decoder components and a small overhead for the control circuitry. Implementation examples show that due to the pipeline strategy, data rates up to 1.28 Gbit/s are reached in a 0.5 μm CMOS technology View full abstract»

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  • Microwave CMOS-device physics and design

    Page(s): 277 - 285
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    This paper discusses design issues and the microwave properties of CMOS devices. A qualitative understanding of the microwave characteristics of MOS transistors is provided. The paper is directed toward helping analog IC circuit designers create better front end radio-frequency CMOS circuits. The network properties of CMOS devices, the frequency response, and the microwave noise properties are reviewed, and a summary of the microwave scaling rules is presented View full abstract»

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  • CMOS technology-year 2010 and beyond

    Page(s): 357 - 366
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    MOS large-scale-integration circuits (LSIs), having advanced remarkably during the past 25 years, are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 μm. In this paper, the anticipated difficulties and some concepts for 0.1- and sub-0.1 μm LSIs are explained based on the research of the downsizing MOSFET into such a dimension, and a further concept for deep sub-0.1-μm LSIs is described View full abstract»

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  • GSM transceiver front-end circuits in 0.25-μm CMOS

    Page(s): 292 - 303
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    So far, CMOS has been shown to be capable of operating at radio-frequency (RF) frequencies, although the inadequacies of the device-level performance often have to be circumvented by innovations at the architectural level that tend to shift the burden to the circuit building blocks at lower frequencies, The RF front-end circuits presented in this paper show that excellent RF performance is feasible with 0.25-μm CMOS, even in terms of the requirements of the tried-and-true superheterodyne architecture. Design for low-noise and low-current consumption targeted for GSM handsets has been given particular attention in this paper. Low-noise amplifiers with sub-2-dB noise figures (NFs) and a double balanced mixer with 12.6 dB single-sideband NF, as well as sub-25-mA current consumption for the RF front end (complete receiver), are among the main achievements View full abstract»

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  • A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

    Page(s): 372 - 379
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    A nonfeedback CMOS digital-clock-generator, direct-skew-detect synchronous-mirror-delay (direct SMD) circuit has been developed that achieves clock-skew suppression in only two clock cycles for application-specific integrated circuits having unfixed and various clock paths. The direct SMD circuit detects both clock skew and clock cycle by using a direct-skew detector and clock-suspension circuitry. The skew-detection scheme removes the phase errors caused by delay in the clock-driver circuit. Measurements demonstrated that the direct SMD circuit eliminates various amounts of clock skew (2.0-3.0 ns) at 200 MHz in two clock cycles View full abstract»

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  • Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations

    Page(s): 304 - 317
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    An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples View full abstract»

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  • A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digital wireless communication

    Page(s): 286 - 291
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    A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC consisting of receive, transmit, and local oscillator (LO) sections is presented. The transmit section achieves an unwanted sideband suppression of -43 dBc, LO leakage of -59 dBc, and third-order spurious rejection of -70 dBc. The transmit output noise level is -165 dBc/Hz at a 20-MHz offset from the carrier. The on-chip very high-frequency oscillator has a phase-noise level of -106 dBc/Hz at 100-kHz offset when operating at 800 MHz. The receive section has 36 dB of gain with 36 dB of gain range in 12-dB steps. The transceiver IC has been fabricated using a 25-GHz ft silicon bipolar process and is designed to operate over a supply-voltage range of 2.7-5.0 V View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan