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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 12 • Date Dec. 1998

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Displaying Results 1 - 14 of 14
  • Author index

    Publication Year: 1998 , Page(s): 1618 - 1623
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    Freely Available from IEEE
  • Subject index

    Publication Year: 1998 , Page(s): 1623 - 1639
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    Freely Available from IEEE
  • Systematic design for optimization of high-speed self-calibrated pipelined A/D converters

    Publication Year: 1998 , Page(s): 1513 - 1526
    Cited by:  Papers (29)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions View full abstract»

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  • The use of unipolar loop signals in the error diffusion modulator

    Publication Year: 1998 , Page(s): 1597 - 1599
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    The error diffusion architecture allows analog to digital conversion provided a bipolar representation is used in the signal processing. In cases when unipolar signal processing is used, the usual architecture must be modified. Changing the usual quantization threshold of the one bit quantizer within the architecture is sufficient when the ratio of the output levels of the quantizer is two or less. When the ratio exceeds two then the range of the input signal must be specially restricted. This work has applications in unipolar signal processing such as NMOS and optical signal processing View full abstract»

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  • CMOS transconductance multipliers: a tutorial

    Publication Year: 1998 , Page(s): 1550 - 1563
    Cited by:  Papers (106)  |  Patents (1)
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    Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been available for some time, the CMOS multiplier implementation is still a challenging subject especially for low-voltage and low-power circuit design. Despite the large number of papers proposing new CMOS multiplier structures, they can be roughly grouped into a few categories. This tutorial provides a complete survey of CMOS multipliers, presents a unified generation of multiplier architectures, and proposes the most recommended MOS multiplier structure. This tutorial could serve as a starting reference point (and metric) for comparison of new CMOS multiplier circuit configurations. An illustrative CMOS chip prototype verifying theoretical results is presented View full abstract»

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  • An analysis of the partial randomization dynamic element matching technique

    Publication Year: 1998 , Page(s): 1538 - 1549
    Cited by:  Papers (5)  |  Patents (3)
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    Partial randomization dynamic element matching (DEM) was recently introduced as a promising DEM technique for low harmonic distortion digital-to-analog conversion. The DEM technique is well suited to applications such as direct digital synthesis in wireless communication systems for which low hardware complexity is essential in addition to low harmonic distortion. Previously reported simulation results demonstrate that partial randomization DEM greatly attenuates harmonic distortion resulting from static errors in the analog output levels of the DAC, while offering considerable savings in hardware compared to other DEM techniques. This paper presents the first quantitative performance analysis of partial randomization DEM. As a main result, the minimum spurious-free dynamic range provided by the digital-to-analog converter has been quantified as a function of its hardware complexity and the analog output level errors View full abstract»

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  • Frequency-response masking approach for the synthesis of sharp two-dimensional diamond-shaped filters

    Publication Year: 1998 , Page(s): 1573 - 1584
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    The frequency-response masking (FRM) technique is an efficient method for realizing sharp one-dimensional (1-D) filters. Sharp 1-D filters realized using the FRM technique have considerably lower complexity than those realized in the direct form. In this paper, we present an extension of the FRM technique to the synthesis of sharp two-dimensional (2-D) diamond-shaped (DS) filters. The new technique, based upon dividing the frequency spectrum into four complementary components and the utilization of four masking filters, achieves large reductions in filter implementation complexity when the transition width of the desired DS filter is very narrow. An expression for the impulse response up-sampling ratio that produces the design with the least complexity is derived. Extensions of the technique for the synthesis of 2-D filters other than the DS filters are also discussed View full abstract»

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  • Convergence of a Hebbian-type learning algorithm

    Publication Year: 1998 , Page(s): 1599 - 1601
    Cited by:  Papers (3)
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    A Hebbian-type learning algorithm was proposed by Gao et al. (1994) for extracting the minor components of the input signals. In this paper, we demonstrate that some solutions of the averaging differential equation of this algorithm can become unbounded in a finite time. We derive five sufficient conditions to ensure that the solutions of its averaging differential equation are bounded and can be extended to the time interval [0, ∞]. Any one of these conditions can guarantee that this algorithm can be used to find the minor components of the input signals View full abstract»

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  • An 8-bit CMOS 3.3-V 65-MHz digital-to-analog converter with a symmetric two-stage current cell matrix architecture

    Publication Year: 1998 , Page(s): 1605 - 1609
    Cited by:  Papers (6)
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    This paper describes a 3.3-V-65-MHz 8-bit CMOS digital-to-analog converter (DAC) with two-stage current cell matrix architecture which consists of a 4-MSB and a 4-LSB current matrix stage. The symmetric two-stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also the number of high swing cascode current mirrors. The designed DAC with an active chip area of 0.8 mm2 is fabricated by a 0.8-μm CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and integral nonlinearity/differential nonlinearity (INL/DNL) are 6 ns, 16 ns, and less than 0.8 LSB, respectively. The designed DAC is fully operational for the power supply down to 2.0 V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3 V is measured to be 34.5 mW View full abstract»

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  • An adaptive technique for modeling second-order Volterra systems with sparse kernels

    Publication Year: 1998 , Page(s): 1610 - 1615
    Cited by:  Papers (4)
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    This paper proposes a simple technique for modeling second-order Volterra systems using an adaptive second-order Volterra delay filter (ASOVDF). The developed filter structure essentially extends an adaptive FIR delay filter to include linear and quadratic filter coefficients with an input assumed to be a zero-mean i.i.d. sequence with a symmetric distribution. The implementation of the ASOVDF is based on a stage-by-stage modeling process. At each stage, a dominant delay element is determined, the corresponding adaptive filter coefficient is incorporated to the adaptive filter coefficients from previous stages, and then these filter coefficients are adapted via the recursive least-squares algorithm. The ASOVDF requires few filter coefficients and has better performance and less computational complexity over the conventional adaptive second-order Volterra filter (ASOVF) in modeling second-order Volterra systems with sparse kernels View full abstract»

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  • A new synthesis procedure for a class of cellular neural networks with space-invariant cloning template

    Publication Year: 1998 , Page(s): 1601 - 1605
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    This paper presents a new synthesis procedure (design algorithm) for cellular neural networks (CNN's) with a space-invariant cloning template with applications to associative memories. In the present synthesis procedure, the design problem is formulated as a set of linear inequalities, and the inequalities are solved using the well-known perceptron training algorithm. Then desired memory patterns are given by a set of bipolar vectors, it is guaranteed that a cellular neural network with a space-invariant cloning template can be designed using the design algorithm developed herein. An algorithm is also provided to design CNN's with space-invariant cloning templates and with symmetric connection matrices to guarantee the global stability of the network. Two specific examples are included to demonstrate the applicability of the methodology developed herein View full abstract»

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  • BiCMOS circuits for analog Viterbi decoders

    Publication Year: 1998 , Page(s): 1527 - 1537
    Cited by:  Papers (20)  |  Patents (3)
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    Analog Viterbi decoders are finding widespread use in class-IV partial-response disk drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8 μm BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5 V power supply View full abstract»

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  • Systematic design of high-speed and low-power digit-serial multipliers

    Publication Year: 1998 , Page(s): 1585 - 1596
    Cited by:  Papers (5)  |  Patents (1)
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    Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of the digit-serial architectures is presented based on a novel design methodology. This methodology permits bit-level pipelining of the digit-serial architectures by moving all feedback loops to the last stage of the design. This enables bit-level pipelining of digit-serial architectures, thereby achieving sample speeds close to corresponding bit-parallel multipliers with lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The proposed approach is applied to the design of various multipliers which form the backbone of digital signal processing computations. The results show that for transformed multipliers with smaller digit sizes (⩽4), the singly-redundant multiplier consumes the least power, and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit size for least power consumption in type-I and type-III multipliers is ~√(2W), where W represents the word length. Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in terms of both latency and power consumption View full abstract»

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  • Object-based selection within an analog VLSI visual attention system

    Publication Year: 1998 , Page(s): 1564 - 1572
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    An object-based analog very large-scale integration (VLSI) model of selective attentional processing has been implemented using a standard 2.0-μm CMOS process. This chip extends previous work on modeling a saliency-map-based selection and scanning mechanism to incorporate the ability to group pixels into objects. This grouping, or segmentation, couples the circuitry of the object's pixels to act as a single, larger pixel. The grouping of pixels is dynamic, driven solely by the segmentation criterion at the input. In this demonstration circuit, image intensity has been chosen for the input saliency map and the segmentation is based on spatial low-pass filtering followed by an intensity threshold. We present experimental results from a one-dimensional implementation of the object-based analog VLSI selective-attention system View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope