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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 1999

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Displaying Results 1 - 15 of 15
  • Guest Editorial

    Page(s): 1 - 2
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    Freely Available from IEEE
  • Importance of rapid photothermal processing in defect reduction and process integration

    Page(s): 36 - 43
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    The smaller dimension devices demand a constant reduction in microscopic and macroscopic defects. To be able to meet the demands of the next-generation integrated circuits (IC's), we need to develop processing techniques that can increase performance, reliability and yield. Defect reduction forms the first important goal in this direction. We have identified stress as a good indicator of the defects generated during processing. Rapid photothermal processing is demonstrated as a new thermal process that can effectively replace furnace processing and rapid thermal processing. Considering various process constraints, we have presented a model for process optimization. This approach would lead to improvements in performance, reliability and yield, while reducing processing temperature and processing time. Experimental results showing the effectiveness of rapid photothermal processing are also presented View full abstract»

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  • Fabless-foundry partnership: models and analysis of coordination issues

    Page(s): 44 - 52
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    The fabless-foundry partnership for integrated circuit (IC) manufacturing business is expected to grow from 12% in 1995 to approximately 17% (i.e., $45B) of the total IC market in 2000. The growth of this market will be even more significant for subquarter micron technologies-whose growth is driven by the multimedia industry. The customer base will extend beyond traditional fabless IC companies into vertically integrated IC manufacturers and system vendors. Given the rate of growth and the high technology profile of products, substantial investments in capital, technology, and skilled workforce have to be dedicated and managed effectively for ensuring a successful partnership. In this paper, we outline the potential coordination problems that may arise in such partnerships, and propose a framework for analyzing issues related to yield information sharing and yield improvement. Our analysis indicates that fabless-foundry contracts that are based on a fixed number of good dies, and better yield information are more profitable View full abstract»

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  • Automatic generation of thin film process flows. I. Basic algorithms

    Page(s): 116 - 128
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    This paper is the first in a series of two papers describing the algorithms used in the development of MISTIC (Michigan synthesis tools for integrated circuits). MISTIC is a planar device process compiler that generates process flows for thin film devices from schematics of their structure. This software uses a laboratory specific database of process recipes to produce process flows for a specific set of laboratory resources (furnaces, etchers, lithography equipment, etc.) and generates process statistics that help to choose the most suitable process flow in a comparative manner. The process compiler is augmented by several auxiliary modules: a device builder, process viewer, and database editor thus forming a self-contained process design environment. This paper concentrates on the algorithms used to construct process flows from schematic device representations. The compiler algorithms first extract a directed graph representation of the device organization stored in the form of a restricted square boolean matrix. This matrix is used to generate linear ordered lists of device layers which serve as footprints for the construction of process flows. Process flows are then constructed from these lists through a series of conversions, expansions, and insertions of process steps View full abstract»

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  • Simulation of complete VLSI fabrication processes with heterogeneous simulation tools

    Page(s): 76 - 86
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    An integrated environment for the simulation of VLSI fabrication processes is presented. Emphasis is put on automated operation to achieve maximum efficiency in TCAD deployment. Addressing the increasing number and diversity of process steps in state-of-the-art semiconductor fabrication processes, mechanisms have been devised to support the smooth, automatic interaction of heterogeneous simulation tools with multiple data formats in the context of large-scale experiments for global calibration, device optimization, and yield improvement tasks. For maximum versatility, the operation of the environment is either controlled via a graphical user interface, a batch file, or a combination of the two. It is possible to submit predefined analysis tasks for background execution, while still being able to monitor and control operation and to access and view simulation data interactively. Split-lot experiments are performed on workstation clusters in parallel operation, delivering the desired results in the shortest possible time. The TCAD environment presented offers server functionality for running large number of complex simulations. At the same time, it supports the design and seamless integration into the environment of client task applications View full abstract»

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  • A machine condition transfer function approach to run-to-run and machine-to-machine reproducibility of III-V compound semiconductor molecular beam epitaxial growth

    Page(s): 66 - 75
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    A concept of machine condition transfer function (MCTF) based on the use of in-situ sensor response to intrinsic surface property of the material is proposed to meet the challenge of run-to-run and machine-to-machine reproducibility of optimized growth conditions for III-V compound semiconductor molecular beam epitaxical growth. The variation in the intensity of the specular beam in reflection high-energy electron diffraction from compound semiconductor surface, measured as a function of the temperature and anion pressure prior to growth, is used as the intrinsic surface property for the generation of MCTF's. The mathematical methodology for realizing MCTF's, including the sensor response surface reconstruction and optimal minimization in combination with a composite statistical design for initial estimation, is presented. Numerical evaluation of the developed methodology shows its promise in practice View full abstract»

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  • Using multivariate nested distributions to model semiconductor manufacturing processes

    Page(s): 53 - 65
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    This paper demonstrates the advantages of modeling semiconductor process variability using a multivariate nested distribution. This distribution allows estimation not only of correlation among various model parameters, but also allows each of those variations to he apportioned among the various stages of the process (i.e., wafer-to-wafer, lot-to-lot, etc.). This permits matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching. The technique also provides focus for process improvement efforts into those areas with the maximum potential reward. Test structures have been designed and fabricated to facilitate extraction of the parameters for the multivariate nested distribution. Using data from a sample of these structures, a process model is built and analyzed; Monte Carlo techniques are then employed using SPICE and a probabilistic process model to predict the performance of a multiplying digital-to-analog converter (MDAC), and the results are compared to measured data from fabricated circuits. Simulations performed using a model built using the multivariate nested approach are shown to provide superior results when compared to simulations using currently accepted multivariate normal models View full abstract»

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  • Production data based optimal etch time control design for a reactive ion etching process

    Page(s): 139 - 147
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    This paper addresses the issue of end point detection and etch time control for a reactive ion etch process. Our approach involves the use of neural networks to model the functional relationship between an end point detection signal, as well as various in situ measurements, and the resulting film thickness remaining. An optimization algorithm is then employed to determine the optimal etch time based on the neural network model in order to achieve the desired level of film thickness remaining. This circumvents the need for monitoring and operating on noisy end point detection signals typically associated with conventional detection schemes. Simulation studies based on production data are presented to further demonstrate the associated design procedures and the feasibility of the algorithm. Tested on data from 89 randomly selected wafers, our controller yields a film thickness distribution with the standard deviation of 6.42 Å, a 50% improvement over the scheme currently implemented in production View full abstract»

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  • Effective excursion detection by defect type grouping in in-line inspection and classification

    Page(s): 3 - 10
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    In this paper, a new methodology for effective process excursion monitoring using defect review/classification information is proposed. We introduce a new defect classification scheme, in which relevant defect types that are likely to be caused by the same mechanism or source are grouped into a “defect family”. It is demonstrated that trending by the defect family drastically improves the detection efficiency of killer defect excursion by reducing or eliminating noise resulting from irrelevant benign defects. We compare the risks of missing critical excursions for monitoring by total defect count, killer defect count, and killer defect family, and illustrate the effectiveness of our methodology using data from actual fabline View full abstract»

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  • Modeling of APCVD-doped silicon dioxide deposition process by a modular neural network

    Page(s): 109 - 115
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    This paper describes a methodology based on the combined utilization of both a multisensor system and an optimized artificial neural network that has been applied to equipment utilized for the production of doped silicon dioxide films. The model exhibits an average relative error around 1% in predicting the concentrations of dopants and the thickness of the oxide layer. One of the major benefits of such a predictor is the ability of providing an on-line estimate of the process yield, thus avoiding off-line testing and gaining a significant reduction of risks of wafer loss. The neural model here described is currently utilized as a control tool at the Texas Instruments Avezzano, Italy, plant View full abstract»

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  • Yield modeling based on in-line scanner defect sizing and a circuit's critical area

    Page(s): 26 - 35
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    Wafers containing a large number of defects on any layer should be discarded in order to avoid the cost associated with processing wafers that are unlikely to yield. Normally decisions about scrapping wafers are based on defect counts. However, including the size of defects can improve the accuracy of such dispositions. If the size of defects is taken into account, critical area provides an estimate of the kill ratio associated with defects of a given size, where the critical area of a layer of a circuit is computed from a circuit's layout. In this paper, the accuracy of the sizing of defects by in-line scanners is analyzed. Then, the impact of defect sizing inaccuracy on estimates of layer yield is discussed, and a methodology to more accurately compute layer yield and kill ratios is presented, which calibrates for inaccuracy in defect sizing by in-line scanners View full abstract»

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  • Automatic generation of thin film process flows. II. Recipe generation, flow evaluation, and system framework

    Page(s): 129 - 138
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    This paper is the second in a series of two papers describing the methodology and algorithms used in the development of MISTIC (Michigan synthesis tools for integrated circuits). Part I [see ibid., vol. 12, no. 1, Feb. 1999] discussed the basic topological algorithms used to produce generic sequences of processing steps required for the fabrication of a given device structure. Part II discusses the expansion of these sequences into complete process flows. This procedure involves the selection of specific recipes from a set of available processing resources and the calculation of recipe parameters. These processing resources are stored in a database central to the MISTIC system framework. Since many process flows are generated for a given device, the paper also discusses the calculation of suitable figures of merit. The capabilities of the MISTIC system are demonstrated with a BiCMOS example. The MISTIC system framework which contains the basic compiler and several supporting modules: a device builder, process viewer, and database editor is also presented View full abstract»

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  • Strategy and metrics for wafer handling automation in legacy semiconductor fab

    Page(s): 102 - 108
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    We present a systematic approach for converting a legacy wafer fab from manual wafer handling to fully automatic wafer handling. Our strategy began by quantifying the need for automation in terms of impact on die yield, identifying a seven percent die loss associated with scratches from wafer handling. We then addressed the fundamental changes in production equipment and processes as well as overall fab goals and attitudes that are required to achieve full wafer handling automation. After considering several approaches to staged fab automation, we selected an approach which eliminated all manual handling within specific fab modules, completing the automation within one group of modules before embarking on another module set. In this way, we limited both the initial scope and cost of the project while preparing to leverage its initial successes. This paper summarizes the methodology and metrics found useful for preparing the fab for change, executing the change, and successfully managing the overall project View full abstract»

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  • The application of submicron lithography defect simulation to IC yield improvement

    Page(s): 11 - 25
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    Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosis of defect sources. This paper proposes a methodology for supplementing such experimental work with defect simulation. In particular, it is shown that lithography defect simulation can provide insight into defect mechanisms that cause major distortions in photoresist profiles. The nature of the distorted patterns can assist us in yield improvement efforts, since by comparing simulation results with the observed photoresist profiles on wafers, defect sources may be identified. Several lithography defect diagnosis examples are presented to demonstrate the approach View full abstract»

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  • Inverse model-based real-time control for temperature uniformity of RTCVD

    Page(s): 87 - 101
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    A reduced-order model describing a rapid thermal chemical vapor deposition (RTCVD) process is utilized for real-time model based control for temperature uniformity across the wafer. Feedback is based on temperature measurements at selected points on the wafer surface. The feedback controller is designed using the internal model control (IMC) structure, especially modified to handle systems described by ordinary differential and algebraic equations. The IMC controller is obtained using optimal control theory on singular arcs extended for multi-input systems. Its performance is also compared with one based on the Hirschorn inverse of the model. The proposed scheme is tested with extensive simulations where the full-order model is used to emulate the process. Several cases of significant uncertainty, including model parameter errors, process disturbances, actuator errors, and measurement noise are used to test the robustness of the controller to real life situations. Both controllers succeed in achieving temperature uniformity well within the desirable bounds, even in cases where several sources of uncertainty are simultaneously present with measurement noise View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721