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IEEE Transactions on Computers

Issue 1 • Date Jan 1999

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Displaying Results 1 - 9 of 9
  • Fault tolerance properties of pyramid networks

    Publication Year: 1999, Page(s):88 - 93
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    In this paper, we study the pyramid network (also called pyramid), one of the important architectures in parallel computing, network computing, and image processing. Some properties of pyramid networks are investigated. We determine the line connectivity and the fault diameters in pyramid networks. We show how to construct a path between two nodes in the faulty pyramid networks in polynomial time.... View full abstract»

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  • Low-power divider

    Publication Year: 1999, Page(s):2 - 14
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The general objective of our work is to develop methods to reduce the energy consumption of arithmetic modules while maintaining the delay unchanged and keeping the increase in the area to a minimum. Here, we illustrate some techniques for dividers realized in CMOS technology. The energy dissipation reduction is carried out at different levels of abstraction: from the algorithm level down to the i... View full abstract»

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  • Distributed fault-tolerant ring embedding and reconfiguration in hypercubes

    Publication Year: 1999, Page(s):81 - 88
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    To embed a ring in a hypercube is to find a Hamiltonian cycle through every node of the hypercube. It is obvious that no 2n-node Hamiltonian cycle exists in an n-dimensional faulty hypercube which has at least one faulty node. However, if a hypercube has faulty links only and the number of faulty links is at most n-2, at least one 2n-node Hamiltonian cycle can be found. In th... View full abstract»

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  • A high-speed reduced-size adder under left-to-right input arrival

    Publication Year: 1999, Page(s):76 - 80
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    An efficient parallel adder under left-to-right input arrival is proposed. Making full use of the delay of the input arrival, it produces the sum within a small constant delay after the arrival of the final bits. Its amount of hardware is proportional to the operand length. It can be applied to the quotient conversion in an array divider View full abstract»

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  • A software cost model with warranty and risk costs

    Publication Year: 1999, Page(s):71 - 75
    Cited by:  Papers (79)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB)

    In this paper, a cost model with warranty cost, time to remove each error detected in the software system, and risk cost due to software failure is developed. A software reliability model based on non-homogeneous Poisson process is used. The optimal release policies to minimize the expected total software cost are discussed. A software tool is also developed using Excel and Visual Basic to facilit... View full abstract»

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  • Multiplexer-based array multipliers

    Publication Year: 1999, Page(s):15 - 23
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. Multiplier arrays for positive numbers and numbers in two's complement form based on th... View full abstract»

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  • Improving design dependability by exploiting an open model-based specification

    Publication Year: 1999, Page(s):24 - 37
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    In an open system standards environment, a formal specification can be shared by all of its implementations, which results in the sharing of development cost. This paper presents a specification-based adaptive test case generation (SBATCG) method for generating validation test cases and a specification-based adaptive consistency check generation (SBACCG) method for generating on-line consistency c... View full abstract»

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  • A gracefully degrading massively parallel system using the BSP model, and its evaluation

    Publication Year: 1999, Page(s):38 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The Bulk-Synchronous Parallel (BSP) Model was proposed as a unifying model for parallel computation. By using Randomized Shared Memory (RSM), the model offers an asymptotically optimal emulation of the Parallel Random Access Machine (PRAM). By using the BSP model with RSM, we construct a gracefully degrading massively parallel system using a fault tolerance (FT) scheme that relies on memory duplic... View full abstract»

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  • Bounding pipeline and instruction cache performance

    Publication Year: 1999, Page(s):53 - 70
    Cited by:  Papers (71)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    Predicting the execution time of code segments in real-time systems is challenging. Most recently designed machines contain pipelines and caches. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss dep... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org