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Circuits, Devices and Systems, IEE Proceedings -

Issue 4 • Date Aug 1998

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Displaying Results 1 - 12 of 12
  • General large-signal charge-control equations for the MOSFET drain and source current under nonquasistatic conditions

    Page(s): 236 - 242
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    General large-signal charge-control equations for the drain and source terminal currents of the long-channel MOSFET on a previously proposed recursion relation are presented. These equations are physically derived following Van Nielen's iterative procedure to reveal the relaxation mechanism in the MOSFET channel under nonquasistatic conditions. The relation between the channel charge partitioning model and the general theoretical development is discussed. This makes it possible to put various solution techniques reported for the MOSFET nonquasistatic problem into perspective. Within the theoretical framework of this work, it is observed that, in general, the drain and source currents share a common relaxation time. The general charge-control equations presented in the paper differ from the simple first-order nonquasistatic current equations, in that they incorporate correction terms to account for the otherwise neglected high-order nonquasistatic effects. Quasistatic formulation of these correction terms is used to illustrate their effects on transient response. It is shown that consistency in the introduction of such correction terms to specific models is crucial to the continuity in current values throughout the transient View full abstract»

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  • High-Q gyrator-based monolithic active tunable bandstop filter

    Page(s): 243 - 246
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    A monolithic bandstop active tunable filter has been designed and realised. The filter is based on a gyrator-type active resonator, implemented using only three active devices. The centre frequency of the realised notch filter is around 2.0 GHz, with a tuning range greater than 400 MHz. The chip dimensions are 1.2×1.2 mm2 including coplanar RF test pads. Measured performances of the realised chip include a typical in-band rejection greater than 35 dB over all the operating bandwidth, a stopband span less than 50 MHz, together with an input/output match greater than 14 dB. Positive supply only has been employed View full abstract»

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  • Enzyme transistor circuits

    Page(s): 264 - 270
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    The authors explore the possibility of constructing extremely high-density computing architectures using molecular electronics technology. By employing the of biological new molecules, such as enzymes, new integrated circuit architectures which are essentially free from interconnection problems could be constructed. To clarify the proposed concept, the authors present a functional model of a basic biomolecular switching device called an `enzyme transistor'. The enzyme transistor is, in a sense, an artificial catalyst which selects a specific substrate molecule and transforms it into a specific product. Using this primitive function, various wire-free computing circuits can be realised: examples include biochemical amplifiers for analogue signal processing and basic digital circuits. Addressing the implementation issue, the authors also propose bioelectronic implementation of enzyme transistors View full abstract»

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  • Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

    Page(s): 247 - 253
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    The authors describe the design, integration and characterisation of a bit-level pipelined self-timed multiplier architecture. The differential structure SODS (switched-output differential structure) has been used for computation blocks and the PLCAR structure (protocol and latching controlled by acknowledge and request) for the interface blocks, introduced in an array-based architecture. A 4×4-bit multiplier has been integrated in a 1.0 μm CMOS technology and the proposed architecture has been compared with other asynchronous approaches, showing a considerable improvement, up to 50%, in terms of area, speed and power consumption. Compared with a synchronous approach, the main advantage of the proposed architecture is a lower power consumption below a certain incoming input data rate, but at the expense of area and speed View full abstract»

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  • Generation of second-order single-OTA RC oscillators

    Page(s): 271 - 277
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    A direct and exhaustive method of generating canonic single-amplifier RC oscillators is introduced. Using this method, the `complete categories' of the bandpass-based single-OTA three- and four-node RC canonic oscillators have been generated. The condition of oscillation of the resulting structures can be adjusted independently of the frequency of oscillation (FO) by the active transconductance parameter of the OTA. All the resulting oscillators enjoy low component counts. Three-node oscillators each contain only capacitors and two resistors, and the four-node oscillators each contain only two capacitors and three resistors. The sensitivities (absolute values) of the FO to the active parameter are zero and the sensitivities to the passive elements are all no greater than 1/2 View full abstract»

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  • Advanced physical model for the optimisation of the width of a resistive Schottky barrier field plate

    Page(s): 260 - 263
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    An advanced physical model based on a solution of Laplace's equation for a set of prescribed boundary conditions is developed, which describes the potential distribution across a resistive Schottky-barrier field plate (RESP). The model serves to ascertain an optimised RESP width, for an optimised RESP sheet resistance, for any potential bias. Optimising the width of the RESP for an optimised sheet resistance will enhance the reverse breakdown voltage handling capability of a Schottky-barrier diode whose periphery is terminated by such a structure. Using an optimised RESP structure will reduce the material costs and improve the high-speed operation of diodes which are edge-terminated in this manner View full abstract»

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  • Single-phase diode rectifier with novel passive filter

    Page(s): 254 - 259
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    A novel passive filter for single-phase diode rectifiers is proposed. It is shown that the novel topology maintains high input power factor, high quality input current waveforms and low rectifier current stress. The operation principle of the proposed topology is analysed in detail under the steady state. Relevant input and output current waveforms and the power factor value are derived. Finally, theoretical results have been verified on an experimental model View full abstract»

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  • Programmable canonical switched-capacitor bump equaliser architecture

    Page(s): 285 - 288
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    A digitally programmable switched-capacitor (SC) bump equaliser structure is presented. It can operate with two non-overlapping clock phases and uses two overlapping clock phases, two operational amplifiers and eight capacitor banks to control the central frequency, the bandwidth and the peak voltage gain steps of the bump (and dip) frequency responses. In the design method, the programmable capacitor arrays are tailored to provide exactly the capacitance values required to realise a restricted but useful set of frequency responses. As a result, the performance of the proposed SC equaliser is not sacrificed for programmability. Numerical results are reported to confirm the viability of the proposed design method View full abstract»

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  • Power-oriented partial-scan design approach

    Page(s): 229 - 235
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    Power consumption and testability are two of the major considerations in modern VLSI design. A full-scan method had been used widely in the past, to improve the testability of sequential circuits. Owing to the lower overheads incurred, the partial-scan design has gradually become popular. The authors propose a partial-scan selection strategy which is based on the structural analysis approach and considers the area and power overheads simultaneously. A powerful sample-and-search algorithm is used to find the solution that minimises the user-specified cost function in terms of power and area overheads. The experimental results show that the sample-and-search algorithm derived by the authors can effectively find the best solution of the specified cost function, for almost all circuits, and, on average, the saving of overheads for each specific cost function is significant View full abstract»

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  • Most-significant-bit-first serial/parallel multiplier

    Page(s): 278 - 284
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    Three serial/parallel multipliers are introduced, which both receive the serial input data and produce the serial product in a most-significant-bit-first (MSB-first) fashion, Advantages of using MSB-first multiplication over conventional least-significant-bit-first multiplication include: efficient calculation of MSB-first data from analogue/digital conversion; efficient interfacing with MSB-first algorithms such as square root and division; and simple truncation of the product. The approach does not utilise any special number system, but multiplier architectures both for unsigned and two's complement number representation (both for the direct and the Baugh-Wooley algorithms) are provided View full abstract»

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  • Mutual conversions between generalised arithmetic expansions and free binary decision diagrams

    Page(s): 219 - 228
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1080 KB)  

    Calculation of generalised arithmetic expansions from free binary decision diagrams of incompletely specified Boolean functions is shown. The way of decomposing generalised arithmetic expansion coefficients in terms of cofactors of Boolean functions is presented. Based on the decomposition a second new algorithm to synthesise quasi-optimal free binary diagrams directly from generalised expansion of Boolean functions is developed View full abstract»

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  • Multiple fault diagnosis in analogue circuits using time domain response features and multilayer perceptrons

    Page(s): 213 - 218
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A technique is described for diagnosing multiple faults in analogue circuits from their impulse response function using multilayer perceptrons, in terms of a specific example. A Dirac impulse input to the circuit was simulated, and time domain features of the output response were classified by a system of two multilayer perceptrons to produce accurate numerical fault values View full abstract»

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